®
STA013
STA013B STA013T
MPEG 2.5 LAYER III AUDIO DECODER
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
- All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5
DECODES LAYER III STEREO CHANNELS,
DUAL
CHANNEL,
SINGLE
CHANNEL
(MONO)
SUPPORTING ALL THE MPEG 1 & 2 SAM-
PLING FREQUENCIES AND THE EXTEN-
SION TO MPEG 2.5:
48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III ELEMEN-
TARY COMPRESSED BITSTREAM WITH
DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
SERIAL BITSTREAM INPUT INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C IN-
TERFACE.
SERIAL PCM OUTPUT INTERFACE (I
2
S
AND OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR OUT-
PUT PCM CLOCK GENERATION
LOW POWER CONSUMPTION:
85mW AT 2.4V
CRC CHECK AND SYNCHRONISATION ER-
ROR DETECTION WITH SOFTWARE INDI-
CATORS
I
2
C CONTROL BUS
LOW POWER 3.3V CMOS TECHNOLOGY
10 MHz, 14.31818 MHz, OR 14.7456 MHz
EXTERNAL INPUT CLOCK OR BUILT-IN IN-
DUSTRY STANDARD XTAL OSCILLATOR
DIFFERENT FREQUENCIES MAY BE SUP-
PORTED UPON REQUEST TO STM
APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
SO28
TQFP44
LFBGA64
ORDERING NUMBERS:
STA013$ (SO28)
STA013T$ (TQFP44)
STA013B$ (LFBGA 8x8)
DESCRIPTION
The STA013 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of de-
coding Layer III compressed elementary streams,
as specified in MPEG 1 and MPEG 2 ISO stand-
ards. The device decodes also elementary streams
compressed by using low sampling rates, as speci-
fied by MPEG 2.5.
STA013 receives the input data through a Serial
Input Interface. The decoded signal is a stereo,
mono, or dual channel digital output that can be
sent directly to a D/A converter, by the PCM Out-
put Interface. This interface is software program-
mable to adapt the STA013 digital output to the
most common DACs architectures used on the
market.
The functional STA013 chip partitioning is de-
scribed in Fig.1.
February 2004
1/38
STA013 - STA013B - STA013T
PIN DESCRIPTION
SO28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TQFP44 LFBGA64
29
30
31
32
34
36
38
40
42
44
2
3
5
6
7
8
10
11
12
13
15
19
21
22
24
25
26
27
B5
B4
A4
B3
A1
B2
D4
D1
E2
F2
H1
H3
F3
E4
G4
G5
F5
G6
G7
G8
F7
E7
C8
D7
A7
B6
A5
C5
Pin Name
VDD_1
VSS_1
SDA
SCL
SDI
SCKR
BIT_EN
SRC_INT
SDO
SCKT
LRCKT
OCLK
VSS_2
VDD_2
VSS_3
VDD_3
PVDD
PVSS
FILT
XTO
XTI
VSS_4
VDD_4
TESTEN
SCANEN
RESET
VSS_5
OUT_CLK/
DATA_REQ
O
I
I
I
O
O
I
I/O
I
I
I
I
I
O
O
O
I/O
Type
Function
Supply Voltage
Ground
i
2
C Serial Data + Acknowledge
I
2
C Serial Clock
Receiver Serial Data
Receiver Serial Clock
Bit Enable
Interrupt Line For S.R. Control
Transmitter Serial Data (PCM
Data)
Transmitter Serial Clock
Transmitter Left/Right Clock
Oversampling Clock for DAC
Ground
Supply Voltage
Ground
Supply Voltage
PLL Power
PLL Ground
PLL Filter Ext. Capacitor Conn.
Crystal Output
Crystal Input (Clock Input)
Ground
Supply Voltage
Test Enable
Scan Enable
System Reset
Ground
Buffered Output Clock/
Data Request Signal
CMOS 4mA Output Drive
CMOS Input Pad Buffer
with pull up
CMOS Input Pad Buffer
CMOS Input Pad Buffer
with pull up
CMOS 4mA Output Drive
Specific Level Input Pad
(see paragraph 2.1)
CMOS Input Pad Buffer
CMOS 4mA Output Drive
CMOS Input Pad Buffer
CMOS Input Pad Buffer
CMOS Input Pad Buffer
CMOS Input Pad Buffer
with pull up
CMOS Input Pad Buffer
CMOS 4mA Output Drive
CMOS 4mA Output Drive
CMOS 4mA Output Drive
CMOS Input Pad Buffer
CMOS 4mA Output Drive
PAD Description
Note:
SRC_INT signal is used by STA013 internal software in Broadcast Mode only; in Multimedia mode SRC_INT must be connected to
V
DD
In functional mode TESTEN must be connected to VDD, SCANEN to ground.
4/38
STA013 - STA013B - STA013T
1. ELECTRICAL CHARACTERISTICS:
V
DD
= 2.7V
±0.3V;
T
amb
= 0 to 70°C; Rg = 50Ω unless otherwise
specified
DC OPERATING CONDITIONS
Symbol
V
DD
Power Supply Voltage
Parameter
Value
2.4 to 3.6V
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
I
IL
I
IH
V
esd
Parameter
Low Level Input Current
Without pull-up device
High Level Input Current
Without pull-up device
Electrostatic Protection
Test Condition
V
i
= 0V
V
i
= V
DD
= 3.6V
Leakage < 1µA
Min.
-10
-10
2000
Typ.
Max.
10
10
Unit
µA
µA
V
Note
1
1
2
Note 1:
The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2:
Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
V
ol
V
oh
Parameter
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
High Level Output Voltage
I
ol
= Xma
0.85*V
DD
Test Condition
Min.
0.8*V
DD
0.4V
Typ.
Max.
0.2*V
DD
Unit
V
V
V
V
1, 2
1, 2
Note
Note 1:
Takes into account 200mV voltage drop in both supply lines.
Note 2:
X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol
I
pu
R
pu
Parameter
Pull-up current
Equivalent Pull-up
Resistance
Test Condition
V
i
= 0V; pin numbers 7, 24
and 26; V
DD
= 3V
Min.
-25
Typ.
-66
50
Max.
-125
Unit
µA
kΩ
Note
1
Note 1:
Min. condition: V
DD
= 2.4V, 125°C Min process
Max. condition: V
DD
= 3.6V, -20°C Max.
POWER DISSIPATION
Symbol
PD
Parameter
Power Dissipation
@ V
DD
= 3V
Test Condition
Sampling_freq
≤24
kHz
Sampling_freq
≤32
kHz
Sampling_freq
≤48
kHz
Min.
Typ.
76
79
85
Max.
Unit
mW
mW
mW
Note
5/38
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