74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
Rev. 2 — 21 August 2017
Product data sheet
1
General description
The 74HC165-Q100; 74HCT165-Q100 are 8-bit serial or parallel-in/serial-out shift
registers. The device features a serial data input (DS), eight parallel data inputs (D0 to
D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input
(PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously.
When PL is HIGH data enters the register serially at DS. When the clock enable input
(CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on
CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the
device to be used in HIGH-to-LOW level shifting applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2
Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
–
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
Asynchronous 8-bit parallel load
•
Synchronous serial input
•
Complies with JEDEC standard no. 7A
•
Input levels:
–
For 74HC165-Q100: CMOS level
–
For 74HCT165-Q100: TTL level
•
ESD protection:
–
MIL-STD-883, method 3015 exceeds 2000 V
–
HBM JESD22-A114F exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
3
Applications
•
Parallel-to-serial data conversion
Nexperia
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
4
Ordering information
Package
Temperature
range
Name
SO16
TSSOP16
Table 1. Ordering information
Type number
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
SOT763-1
74HC165D-Q100
74HCT165D-Q100
74HC165PW-Q100
74HCT165PW-Q100
74HC165BQ-Q100
74HCT165BQ-Q100
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
5
Functional diagram
1
15
2
10
11
12
13
14
3
4
5
6
mna985
mna986
SRG8
C2[LOAD]
G1[SHIFT]
≥1
10
11
12
13
14
3
4
5
6
1
DS
D0
D1
D2
D3
D4
D5
D6
D7
PL
CP CE
2
15
Q7
Q7
9
7
1
C3/
3D
2D
2D
9
7
Figure 1. Logic symbol
Figure 2. IEC logic symbol
11 12 13 14 3
4
5
6
D0 D1 D2 D3 D4 D5 D6 D7
1 PL
10 DS
2 CP
15 CE
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
Q7 9
Q7 7
mna992
Figure 3. Functional diagram
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 2 — 21 August 2017
2 / 21
Nexperia
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
6
Pinning information
6.1 Pinning
74HC165-Q100
74HCT165-Q100
terminal 1
index area
16 V
CC
15 CE
14 D3
13 D2
12 D1
GND
(1)
8
9
Q7
11 D0
10 DS
GND
PL
2
3
4
5
6
7
1
74HC165-Q100
74HCT165-Q100
PL
CP
D4
D5
D6
D7
Q7
GND
1
2
3
4
5
6
7
8
aaa-003155
CP
D4
16 V
CC
15 CE
14 D3
13 D2
12 D1
11 D0
10 DS
9
Q7
D5
D6
D7
Q7
aaa-003156
Transparent top view
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Figure 5. Pin configuration (DHVQFN16)
Figure 4. Pin configuration (SO16 and TSSOP16)
6.2 Pin description
Table 2. Pin description
Symbol
PL
CP
Q7
GND
Q7
DS
D0 to D7
CE
V
CC
Pin
1
2
7
8
9
10
11, 12, 13, 14, 3, 4, 5, 6
15
16
Description
asynchronous parallel load input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary output from the last stage
ground (0 V)
serial output from the last stage
serial data input
parallel data inputs (also referred to as Dn)
clock enable input (active LOW)
positive supply voltage
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 2 — 21 August 2017
3 / 21
Nexperia
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
7
Functional description
[1]
Table 3. Function table
Operating modes Inputs
PL
parallel load
serial shift
L
L
H
H
H
H
hold "do nothing"
H
H
[1]
Qn registers
CE
X
X
L
L
↑
↑
H
X
Outputs
Q7
H
L
q6
q6
q6
q6
q7
q7
L
H
q6
q6
q6
q6
q7
q7
CP
X
X
↑
↑
L
L
X
H
DS
X
X
l
h
l
h
X
X
D0 to D7 Q0
L
H
X
X
X
X
X
X
L
H
L
H
L
H
q0
q0
Q1 to Q6 Q7
L to L
H to H
q0 to q5
q0 to q5
q0 to q5
q0 to q5
q1 to q6
q1 to q6
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
↑ = LOW-to-HIGH clock transition.
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit
load
serial shift
mna993
Figure 6. Timing diagram
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 2 — 21 August 2017
4 / 21
Nexperia
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
8
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
-0.5 V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
-0.5
-
-
-
-
-50
-65
Max
+7
±20
±20
±25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
= -40 °C to +125 °C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 Packages: P
tot
derates linearly with 8 mW/K above 70 °C.
For TSSOP16 Packages: P
tot
derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN16 Packages: P
tot
derates linearly with 4.5 mW/K above 60 °C.
9
Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
Conditions
74HC165-Q100
Min
2.0
0
0
-40
74HCT165-Q100
Min
4.5
0
0
-40
-
-
-
Unit
V
V
V
°C
ns/V
ns/V
ns/V
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Typ
5.0
-
-
-
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
-
-
-
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 2 — 21 August 2017
5 / 21
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