4+1 Phase Dual Output Control IC
FEATURES
Integrated 6.8V/0.8A Buck Regulator provides
bias to Control and Driver IC(s)
Adjustable switching frequency from 250 KHz up
to 1.5MHz per phase based on the synchronization
SCLK input
Sink and source tracking capability
Margining via SVID for both rails
Pre-bias compatible
Soft Stop capability
0.5% overall system set point accuracy
Voltage Mode Modulation for excellent transient
performance
Single NTC thermistor for current reporting, OC
Threshold, and Load Line thermal compensation
Complete protection including over-current,
over-voltage, over-temperature, open remote
sense and open control loop
Thermally enhanced 48L 7mm x 7mm MLPQ
package
RoHS compliant
IR3531A
DESCRIPTION
The IR3531A control IC provides all the necessary control,
communication and protection to support compact dual
output power solutions up to 210W. The IR3531A can be
combined with either discrete IR3535 driver ICs and Direct
Fets
TM
or our IR35XX family of footprint compatible and
scalable PowIRstages
TM
which integrate the MOSFETs and
driver into the same package.
The IR3531A provides overall system control and current
sharing while the Driver IC or power stages senses per-
phase current locally and communicates it to the Control
IC. The IR3531A has tri-state PWM outputs to allow diode
emulation during light load events.
The IR3531A provides a high performance transient
solution through classic voltage mode control and Body
Braking
TM
. Body Braking
TM
automatically turns off the low-
side MOSFET to help dissipate stored inductor energy at
load turn-off.
BASIC APPLICATION CIRCUIT
PIN DIAGRAM
VOSEN1+
VOSEN1-
PWM_R1
TRACK1
VDAC1
VDRP1
IIN_R1
VO1
EA1
FB1
IIN4
38
48
EN
VRHOT#
VRRDY1
VRRDY
1
2
3
4
5
6
7
8
9
10
11
47
46
45
44
43
42
41
40
39
37
36
35
34
33
BBR1#
PWM4
PWM3
TSENS
ROSC/OVP
ADDR
ICCP
SCLK
PWM2
PWM1
BBR#
TRACK
A
VCC
SW
V12V
ALERT#
VCLK
VDIO
PHSSHED
IMON_R1
IR3531A
48 Pin 7 x 7 MLPQ
Top View
IIN3
32
31
30
29
28
27
26
25
24
49 GND
12
13
14
15
16
17
18
19
20
21
22
23
VOSEN+
PSC
FB
VDRP
VO
VOSEN-
EA
IIN1
VDAC
Figure 1: IR3531A Basic Application Circuit,
showing a 4+1 Configuration
1
March 22, 2012 | FINAL | V1.11
IMON
Figure 2: IR3531A Package Top View
IIN2
VN
4+1 Phase Dual Output Control IC
ORDERING INFORMATION
IR3531A
―
M
Package
48 Lead MLPQ
(7x7 mm body)
PBF
– Lead Free
TR
– Tape and Reel
IR3531A
Tape & Reel Qty
100
3000
Part Number
IR3531A-MPBF
IR3531A-MTRPBF
1
48 Lead MLPQ
(7x7 mm body)
Note :
Samples only.
1
VOSEN1+
VOSEN1-
PWM_R1
TRACK1
VDAC1
VDRP1
IIN_R1
VO1
EA1
FB1
IIN4
38
48
EN
VRHOT#
VRRDY1
VRRDY
VCC
SW
V12V
ALERT#
VCLK
VDIO
PHSSHED
IMON_R1
1
2
3
4
5
6
7
8
9
10
11
47
46
45
44
43
42
41
40
39
37
36
35
34
33
BBR1#
PWM4
PWM3
TSENS
ROSC/OVP
ADDR
ICCP
SCLK
PWM2
PWM1
BBR#
TRACK
IR3531A
48 Pin 7 x 7 MLPQ
Top View
IIN3
32
31
30
29
28
27
26
25
24
49 GND
12
13
14
15
16
17
18
19
20
21
22
23
VOSEN+
PSC
FB
VDRP
VO
VOSEN-
EA
IIN1
VDAC
IMON
Figure 3: Package Top View, Enlarged
2
March 22, 2012 | FINAL | V1.11
IIN2
VN
4+1 Phase Dual Output Control IC
FUNCTIONAL BLOCK DIAGRAM
IR3531A
Figure 4: IR3531A Block Diagram
3
March 22, 2012 | FINAL | V1.11
4+1 Phase Dual Output Control IC
TYPICAL APPLICATION DIAGRAM
RCP1
CCP1
RCFB1
CFB1
VOSEN1+
VOSEN1-
TRACK1
IR3531A
RFB1
CEA1
TO IOUT SIGNALS
OF PHASES 3, 4
PWM4
PWM3
IIN4
IIN3
RDRP1
BBR1#
TO PWM SIGNALS
OF PHASES 3, 4
RAIL1
SIGNALS
VDAC1
RSCALE3
RSCALE2
RSCALE1
RTHERM3
IOUT1
48
47
46
45
44
43
42
41
40
39
38
IIN4
PWM_R1
VOSEN1+
VDRP1
VDAC1
VO1
VOSEN1-
IIN_R1
PWM_R1
TRACK1
IIN3
EA1
FB1
37
RHOTSET2
36
35
RHOTSET1
34
33
32
ROSC
31
30
29
28
27
26
25
PWM2
PWM1
BBR#
TRACK
IIN2
RICCP1
RICCP2
SCLK
RADDR2
RADDR1
VDAC
RTHERM2
RHOTSET3
VDAC
ENABLE
VRHOT#
VRRDY 1
VRRDY
LVCC
1
2
12V
COUTVCC
ALERT#
VCLK
VDIO
PHSSHED
1
2
3
4
5
6
7
8
9
10
11
12
EN
BBR1#
PWM4
PWM3
TSENS
ROSC/OVP
VRHOT#
VRRDY 1
VRRDY
VCC
SW
V12V
ALERT#
VCLK
VDIO
PHSSHED
VOSEN-
IR3531A
ADDR
ICCP
SCLK
PWM2
PWM1
BBR#
VOSEN+
IMON_R1
VDRP
VDAC
IMON
PSC
TRACK
IIN1
IIN2
TO PWM SIGNALS
OF PHASES 1, 2
CIMON1
49
GND
13
14
15
16
17
18
19
20
VO
VN
FB
EA
21
22
23
CIMON
RTCMP3
VDAC
IIN1
24
TO IOUT SIGNALS
OF PHASES 1, 2
RPSC
RCP
CCP
VOSEN+
RTCMP1
RTHERM1
CEA
RFB
RTCMP2
RDRP
Figure 5: IR3531A Typical Application Diagram
4
March 22, 2012 | FINAL | V1.11
VOSEN-
RCFB
CFB
4+1 Phase Dual Output Control IC
PIN DESCRIPTIONS
PIN #
1
2
3
4
5
6
7
8
9
IR3531A
PIN NAME
EN
VRHOT#
VDRRY1
VDRRY
VCC
SW
V12V
ALERT#
VCLK
PIN DESCRIPTION
Enable input. Grounding this pin shuts down the voltage regulators. Do not float this pin as the
logic state will be undefined.
Open collector output of the VRHOT# comparator which drives low if Rail0 temperature exceeds
the programmed threshold. Connect external pull-up to bias.
Open collector output that drives low during startup and under any external fault condition for
Rail1 regulator. Connect external pull-up to bias.
Open collector output that drives low during startup and under any external fault condition for
Rail0 regulator. Connect external pull-up to bias.
Bias buck regulator output, feedback pin, and bias input for internal circuitry.
Switching node for bias buck regulator.
Power Supply input supply rail.
Output pin for SVID Alert# interrupt. Open collector output that drives low to notify the master.
SVID Clock Input. Clock is a high impedance input pin. It is driven by the open collector output of a
microprocessor and requires a pull-up resistor.
SVID Data Input/Output. High impedance input when address, command or data bits are shifted in,
open drain output when acknowledging or sending data back to the microprocessor. Pin requires a
pull up resistor.
Analog signal that represents the number of phases to be disabled. 0% to 25% VCC, no phases
disabled. 25% to 50% VCC, disable 1 phase. 50% to 75% VCC, disable 2 phases. 75% to 100% VCC,
disable 3 phases (if available).
Voltage at this pin is proportional to Rail1 load current. It is also the input to the ADC for output
current register.
Voltage at this pin is proportional to Rail0 load current. It is also the input to the ADC for output
current register.
Voltage Regulator Rail 0 reference voltage programmed by SVID. VDAC is also used as the A/D
reference during power up for pins ADDR/PSN, TSENS and ICCP.
Node for DCR thermal compensation network.
Buffered, scaled and thermally compensated current signal for Rail0. Connect an external resistor
to FB to program converter output impedance.
Output of the error amplifier for Rail0.
Node for Power Savings mode compensation input.
Inverting input to the Error Amplifier for Rail0.
Remote sense amplifier output for Rail0.
Rail0 remote sense amplifier input. Connect to output at the load.
Rail0 remote sense amplifier input. Connect to ground at the load.
Current signals from the driver IC-s of Rail0.
External tracking reference for Rail0.
Body-braking
TM
bus for Rail0 driver ICs to disable synchronous switches.
PWM outputs for Rail0. Each output is connected to the input of the driver IC. Connecting the
PWMx output to LGND disables the phase, allowing the IR3531A to operate as a 1, 2, 3, or 4 phase
controller.
Synchronization clock input. Program ROSC using ROSC vs. Frequency to match the SCLK frequency.
10
VDIO
11
PHSSHED
12
13
14
15
16
17
18
19
20
21
22
23, 24, 37, 38
25
26
27, 28,
34, 35
29
IMON_R1
IMON
VDAC
VN
VDRP
EA
PSC
FB
VO
VOSEN+
VOSEN-
IIN1-4
TRACK
BBR#
PWM1-4
SCLK
5
March 22, 2012 | FINAL | V1.11
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