MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
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•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
All Outputs Buffered
•
Capable of Driving Two Low−power TTL Loads or One Low−power
•
•
•
•
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
MARKING DIAGRAMS
14
140xxBG
AWLYWW
1
SOIC−14
xx
A
WL, L
YY, Y
WW, W
G or
G
1
TSSOP−14
14
14
0xxB
ALYWG
G
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
V
ESD
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
ESD Withstand Voltage
Human Body Model
Machine Model
Charged Device Model
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±
10
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
mW
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
DEVICE INFORMATION
Device
Description
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
Triple 3−Input NAND Gate
Triple 3−Input NOR Gate
Quad 2−Input OR Gate
Triple 3−Input AND Gate
Quad 2−Input AND Gate
Dual 4−Input AND Gate
°C
°C
°C
V
MC14001B
MC14011B
MC14023B
MC14025B
MC14071B
MC14073B
MC14081B
MC14082B
> 3000
> 300
N/A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 11
Publication Order Number:
MC14001B/D
MC14001B Series
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
− 55_C
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
V
IH
5.0
10
15
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
−
−
−
−
−
−
−
±0.1
−
0.25
0.5
1.0
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
5.0
0.0005
0.0010
0.0015
−
−
−
−
−
−
−
±0.1
7.5
0.25
0.5
1.0
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
−
−
−
−
−
−
−
±1.0
−
7.5
15
30
mAdc
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
mAdc
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Min
−
−
−
4.95
9.95
14.95
−
−
−
25_C
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
125_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Vdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
“0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Gate, C
L
= 50 pF)
V
OH
Vdc
V
IL
Vdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
I
T
I
T
= (0.3
mA/kHz)
f + I
DD
/N
I
T
= (0.6
mA/kHz)
f + I
DD
/N
I
T
= (0.9
mA/kHz)
f + I
DD
/N
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
− 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
− V
SS
) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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3
MC14001B Series
B−SERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS
(Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Output Rise Time, All B−Series Gates
t
TLH
= (1.35 ns/pF) C
L
+ 33 ns
t
TLH
= (0.60 ns/pF) C
L
+ 20 ns
t
TLH
= (0.40 ns/PF) C
L
+ 20 ns
Output Fall Time, All B−Series Gates
t
THL
= (1.35 ns/pF) C
L
+ 33 ns
t
THL
= (0.60 ns/pF) C
L
+ 20 ns
t
THL
= (0.40 ns/pF) C
L
+ 20 ns
Propagation Delay Time
MC14001B, MC14011B only
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 80 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 32 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 27 ns
All Other 2, 3, and 4 Input Gates
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 115 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 47 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 37 ns
8−Input Gates (MC14068B, MC14078B)
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 155 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 62 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 47 ns
Symbol
t
TLH
5.0
10
15
t
THL
5.0
10
15
t
PLH
, t
PHL
5.0
10
15
5.0
10
15
5.0
10
15
−
−
−
−
−
−
−
−
−
125
50
40
160
65
50
200
80
60
250
100
80
300
130
100
350
150
110
−
−
−
100
50
40
200
100
80
ns
−
−
−
100
50
40
200
100
80
ns
V
DD
Vdc
Min
Typ
(Note 6)
Max
Unit
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
14
INPUT
V
DD
20 ns
INPUT
OUTPUT
t
PHL
OUTPUT
INVERTING
90%
50%
10%
t
THL
t
PLH
90%
50%
10%
20 ns
V
DD
0V
t
PLH
V
OH
t
TLH
t
PHL
90%
50%
10%
V
OL
V
OH
V
OL
PULSE
GENERATOR
*
C
L
7
V
SS
*All unused inputs of AND, NAND gates must be connected to V
DD
.
All unused inputs of OR, NOR gates must be connected to V
SS
.
OUTPUT
NON-INVERTING
t
TLH
t
THL
Figure 1. Switching Time Test Circuit and Waveforms
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