xr
MAY 2005
ST16C2450
2.97V TO 5.5V DUART
REV. 4.0.1
GENERAL DESCRIPTION
The ST16C2450 (2450) is a dual universal asynchro-
nous receiver and transmitter (UART). The
ST16C2450 is an improved version of the
ST16C2450 with lower operating voltage and 5 volt
tolerant inputs. The 2450 provides enhanced UART
functions, a modem control interface and data rates
up to 1.5 Mbps. Onboard status registers provide the
user with error indications and operational status. In-
dependent programmable baud rate generators are
provided to select transmit and receive clock rates up
to 1.5 Mbps. An internal loopback capability allows
onboard diagnostics. The 2450 is available in a 44-
pin PLCC and 48-pin TQFP packages. The 2450 is
fabricated in an advanced CMOS process capable of
operating from 2.97 volt to 5.5 volt power supply. The
devices with a top marking of "A2 YYWW" or newer
have 5 volt tolerant inputs.
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. ST16C2450 B
LOCK
D
IAGRAM
FEATURES
Added feature in devices with top marking "A2
YYWW" and newer:
■
5 Volt Tolerant Inputs
•
2.97 to 5.5 Volt Operation
•
Pin-to-pin compatible to Exar’s XR16C2450,
ST16C2550,
XR16C2850
■
■
■
■
■
■
XR16L2550,
XR16L2750
and
•
2 independent UART channels
Up to 1.5 Mbps data rate with a 24 MHz crystal
oscillator or external clock frequency
1 byte Transmit FIFO
1 byte Receive FIFO with error tags
Status report registers
Modem control signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
•
Crystal oscillator or external clock input
•
TTL compatible inputs, outputs
•
Industrial temperature ranges
•
48-TQFP and 44-PLCC packages
*5V Tolerant inputs
2.97 to 5.5 Volt VCC
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
8-bit Data
Bus
Interface
UART Channel A
UART
Regs
THR
RHR
Modem I/Os
TXA
RXA
RTSA#, CTSA#,
DTRA#, DSRA#,
CDA#, RIA#, OP2A#
TXB
RXB
RTSB#, CTSB#,
DTRB#, DSRB#,
CDB#, RIB#, OP2B#
XTAL1
XTAL2
BRG
UART Channel B
(same as Channel A)
Reset
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
ST16C2450
2.97V TO 5.5V DUART
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
DSRA#
CTSA#
CDA#
xr
REV. 4.0.1
VCC
NC
RIA#
48
45
43
42
41
40
38
47
46
44
39
37
NC
D4
D3
D2
D1
D0
D5
D6
D7
RXB
RXA
NC
TXA
TXB
OP2B#
1
2
3
4
5
6
7
8
9
36
35
34
33
RESET
DTRB#
DTRA#
RTSA#
OP2A#
NC
INTA
INTB
A0
A1
A2
NC
ST16C2450
48-pin TQFP
32
31
30
29
28
27
26
25
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
40
39
38
37
36
35
34
VCC
RIA#
CDA#
DSRA#
CTSA#
RESET
DTRB#
DTRA#
RTSA#
OP2A#
INTA
INTB
A0
A1
A2
CTSB#
RTSB#
RIB#
DSRB#
IOR#
CSA# 10
CSB# 11
NC 12
15
13
18
19
20
22
16
14
17
21
23
24
GND
NC
XTAL2
RTSB#
DSRB#
CTSB#
CDB#
IOW#
XTAL1
IOR#
RIB#
NC
D5
D6
D7
DSRA#
CTSA#
RXB
RXA
TXA
39
38
37
36
RESET
DTRB#
DTRA#
RTSA#
9
10
11
12
13
14
15
16
17
18
19
20
ST16C2450CP40
8
33
32
31
30
29
28
27
26
25
24
23
22
21
44
43
42
CDA#
RIA#
VCC
NC
D4
D3
D2
D1
D0
41
40
6
5
4
3
2
1
D5
D6
D7
RXB
RXA
7
8
9
10
11
TXB
OP2B#
CSA#
CSB#
XTAL1
XTAL2
IOW#
CDB#
GND
NC 12
TXA
TXB
13
14
ST16C2450
44-pin PLCC
35 OP2A#
34
33
32
31
NC
INTA
INTB
A0
OP2B# 15
CSA# 16
CSB# 17
XTAL1 18
XTAL2 19
IOW# 20
21
GND 22
23
IOR# 24
DSRB# 25
RIB# 26
RTSB# 27
CTSB# 28
30 A1
29
A2
ORDERING INFORMATION
O
PERATING
P
ART
N
UMBER
ST16C2450CP40
ST16C2450CJ44
P
ACKAGE
40-Lead PDIP
44-Lead PLCC
T
EMPERATURE
R
ANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active. See the ST16C2450CQ48 for new designs.
Active
Active
Active. See the ST16C2450IQ48 for new designs.
Active
Active
ST16C2450CQ48 48-Lead TQFP
ST16C2450IP40
ST16C2450IJ44
ST16C2450IQ48
40-Lead PDIP
44-Lead PLCC
48-Lead TQFP
CDB#
NC
2
xr
REV. 4.0.1
ST16C2450
2.97V TO 5.5V DUART
PIN DESCRIPTIONS
Pin Description
N
AME
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
29
30
31
9
8
7
6
5
4
3
2
24
26
27
28
3
2
1
48
47
46
45
44
19
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
Data bus lines [7:0] (bidirectional).
IO
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
UART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default).
UART channel B Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0 (default).
IOW#
20
15
I
CSA#
CSB#
INTA
16
17
33
10
11
30
I
I
O
INTB
32
29
O
MODEM OR SERIAL I/O INTERFACE
TXA
RXA
13
11
7
5
O
I
UART channel A Transmit Data. If it is not used, leave it unconnected.
UART channel A Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
UART channel A Request-to-Send (active low) or general purpose out-
put. If it is not used, leave it unconnected.
UART channel A Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
RTSA#
CTSA#
36
40
33
38
O
I
3
ST16C2450
2.97V TO 5.5V DUART
Pin Description
N
AME
DTRA#
DSRA#
44-PLCC
P
IN
#
37
41
48-TQFP
P
IN
#
34
39
T
YPE
O
I
D
ESCRIPTION
xr
REV. 4.0.1
UART channel A Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
Output Port 2 Channel A - The output state is defined by the user and
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTA output functionality. If it is not used at all, leave it
unconnected.
UART channel B Transmit Data. If it is not used, leave it unconnected.
UART channel B Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
UART channel B Request-to-Send (active low) or general purpose out-
put. If it is not used, leave it unconnected.
UART channel B Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTB output functionality. If it is not used, leave it uncon-
nected.
CDA#
42
40
I
RIA#
43
41
I
OP2A#
35
32
O
TXB
RXB
14
10
8
4
O
I
RTSB#
CTSB#
27
28
22
23
O
I
DTRB#
DSRB#
38
25
35
20
O
I
CDB#
21
16
I
RIB#
26
21
I
OP2B#
15
9
O
4
xr
REV. 4.0.1
ST16C2450
2.97V TO 5.5V DUART
Pin Description
N
AME
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
18
19
39
13
14
36
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output
will be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period.
2.97V to 5.5V power supply. All inputs are 5V tolerant for devices with
top marking of "A2 YYWW" and newer.
Power supply common, ground.
No Connection. These pins are open, but typically, should be con-
nected to GND for good design practice.
VCC
GND
N.C.
44
22
1, 12, 23,
34
42
17
6, 12, 18,
24, 25, 31,
37, 43
Pwr
Pwr
-
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
1.0 PRODUCT DESCRIPTION
The ST16C2450 (2450) integrates the functions of two 16C450 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The 2450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-
parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The 2450 represents such an integration with greatly enhanced features. The 2450 is fabricated with an
advanced CMOS process. The 2450 is capable of operation up to 1.5 Mbps with a 24 MHz clock. With a crystal
or external clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2450 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C450 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in
Figure 3.
5
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