MC74HC03A
Quad 2-Input NAND Gate
with Open-Drain Outputs
High−Performance Silicon−Gate CMOS
The MC74HC03A is identical in pinout to the LS03. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC03A NAND gate has, as its outputs, a high−performance
MOS N−Channel transistor. This NAND gate can, therefore, with a
suitable pullup resistor, be used in wired−AND applications. Having
the output characteristic curves given in this data sheet, this device can
be used as an LED driver or in any other application that only requires
a sinking current.
Features
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MARKING
DIAGRAMS
14
14
1
SOIC−14
D SUFFIX
CASE 751A
1
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
A
L, WL
Y, YY
W, WW
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
HC
03A
ALYWG
G
HC03AG
AWLYWW
•
Output Drive Capability: 10 LSTTL Loads With Suitable Pullup
•
•
•
•
•
•
•
•
Resistor
Outputs Directly Interface to CMOS, NMOS and TTL
High Noise Immunity Characteristic of CMOS Devices
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1
mA
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 28 FETs or 7 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
V
CC
OUTPUT
PROTECTION
DIODE
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
Z
Z
Z
L
PIN 14 = V
CC
PIN 7 = GND
* Denotes open-drain outputs
3,6,8,11
Y*
Z = High Impedance
A
B
1,4,9,12
2,5,10,13
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Pinout: 14−Lead Packages
(Top View)
V
CC
14
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
1
A1
2
B1
3
Y1
4
A2
5
B2
6
Y2
7
GND
©
Semiconductor Components Industries, LLC, 2013
October, 2013
−
Rev. 13
1
Publication Order Number:
MC74HC03A/D
MC74HC03A
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MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
V
out
I
out
P
D
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Output Current, per Pin
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±
20
±
25
±
50
500
450
mA
mA
mA
I
CC
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Storage Temperature
SOIC Package
†
TSSOP Package
†
mW
°C
°C
T
stg
T
L
–65 to + 150
260
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating
−
SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package:
−
6.1 mW/°C from 65° to 125°C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
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Symbol
V
CC
T
A
V
in
, V
out
t
r
, t
f
Parameter
Min
2.0
0
0
0
0
Max
6.0
V
CC
Unit
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
–55
+125
1000
500
400
°C
ns
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
RECOMMENDED OPERATING CONDITIONS
DESIGN GUIDE
Criteria
Value
7.0
1.5
5.0
Unit
ea
ns
mW
pJ
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate
0.0075
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2
MC74HC03A
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Condition
V
out
= 0.1V or V
CC
−0.1V
|I
out
|
≤
20mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
6.0
Guaranteed Limit
−55
to 25°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
1.0
±0.5
≤85°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
10
±5.0
≤125°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
0.1
0.1
0.1
0.40
0.40
0.40
±1.0
40
±10
mA
mA
mA
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
out
= 0.1V or V
CC
−
0.1V
|I
out
|
≤
20mA
V
V
OL
Maximum Low−Level Output
Voltage
V
out
= 0.1V or V
CC
−
0.1V
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
V
I
in
I
CC
I
OZ
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
Maximum Three−State Leakage
Current
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0mA
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
t
PLZ
,
t
PZL
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
−55
to 25°C
120
45
24
20
75
27
15
13
10
10
≤85°C
150
60
30
26
95
32
19
16
10
10
≤125°C
180
75
36
31
110
36
22
19
10
10
Unit
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ns
C
in
C
out
Maximum Input Capacitance
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
pF
pF
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
8.0
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
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3
MC74HC03A
V
CC
t
r
INPUT A
90%
50%
10%
t
PZL
OUTPUT Y
90%
50%
10%
t
THL
t
PLZ
t
f
V
CC
GND
HIGH
IMPEDANCE
10%
V
OL
*Includes all probe and jig capacitance
DEVICE
UNDER
TEST
1kW
OUTPUT
R
pd
TEST
POINT
C
L
*
Figure 1. Switching Waveforms
25
TYPICAL
T=25°C
20
I D, SINK CURRENT (mA)
T=25°C
15
T=85°C
10
T=125°C
EXPECTED MINIMUM*
5
V
CC
=5V
Figure 2. Test Circuit
0
0
1
2
3
4
V
O
, OUTPUT VOLTAGE (VOLTS)
5
*The expected minimum curves are not guarantees, but are design aids.
Figure 3. Open−Drain Output Characteristics
V
CC
PULLUP
RESISTOR
A1
B1
A2
B2
1/4
HC03
1/4
HC03
Y1
V
CC
+
V
R
-
+
V
F
-
LED1
1/4
HC03
1/4
HC03
V
CC
OUTPUT
Y2
LED2
LED
ENABLE
DESIGN EXAMPLE
CONDITIONS: I
D
^10mA
TYPICAL CURVE, at I
D
=10mA,
V
DS
^0.4V
V
*
VF
*
VO
NR +
CC
ID
+
5V
*
1.7V
*
0.4V
10mA
+
290W
USE R = 270W
An
Bn
1/4
HC03
Yn
OUTPUT = Y1
•
Y2
•
. . .
•
Yn
= A1B1
•
A2B2
•
. . .
•
AnBn
Figure 4. Wired AND
Figure 5. LED Driver With Blanking
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4
MC74HC03A
ORDERING INFORMATION
Device
MC74HC03ADG
MC74HC03ADR2G
MC74HC03ADTR2G
NLV74HC03ADG*
NLV74HC03ADR2G*
NLV74HC03ADTR2G*
Package
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
TSSOP−14
(Pb−Free)
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
TSSOP−14
(Pb−Free)
Shipping
†
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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5
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