AS4C16M16D1
16M x 16 bit DDR Synchronous DRAM (SDRAM)
Alliance Memory Confidential
Features
Fast clock rate: 200MHz
Differential Clock CK &
CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 4M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte-write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Precharge & active power down
Power supplies: V
DD &
V
DDQ
= 2.5V
0.2V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
- Pb free and Halogen free
Package: 60-Ball, 8x13x1.2 mm (max) TFBGA
- Pb free and Halogen Free
Advanced (Rev. 1.1, Sep. /2011)
Overview
The AS4C16M16D1 SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 256 Mbits.
It is internally configured as a quad 4M x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CK). Data outputs occur
at both rising edges of CK and
CK
.d Read and write
accesses to the SDRAM are burst oriented; accesses start
at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command
which is then followed by a Read or Write command. The
AS4C16M16D1 provides programmable Read or Write
burst lengths of 2, 4, or 8. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use. In
addition, AS4C16M16D1 features
programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring high
memory band-width, result in a device particularly well
suited to high performance main memory and graphics
applications.
Table 1.Ordering Information
Temperature Temp Range
Part Number
Clock
Data Rate
Package
0 ~ 70°C
AS4C16M16D1-5TCN 200MHz 400Mbps/pin 66pin TSOPII Commercial
Industrial
-40 ~ 85°C
AS4C16M16D1-5TIN 200MHz 400Mbps/pin 66pin TSOPII
0 ~ 70°C
AS4C16M16D1-5BCN 200MHz 400Mbps/pin 60ball TFBGA Commercial
Industrial
-40 ~ 85°C
AS4C16M16D1-5BIN 200MHz 400Mbps/pin 60ball TFBGA
T: indicates TSOP II package
B: indicates TFBGA package
C: indicates Commercial temp.
I: indicates Industrial temp.
N: indicates lead free ROHS
Alliance Memory, Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800
FAX: (650) 620-9211
Alliance Memory, Inc. reserves the right to change products or specification without notice.
AS4C16M16D1
Pin Descriptions
Table 2. Pin Details
Symbol
CK,
CK
Type
Input
Description
Differential Clock:
CK,
CK
are driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CK. Both CK and
CK
increment the internal burst
counter and controls the output registers.
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains
low. When all banks are in the idle state, deactivating the clock controls the entry to
the Power Down and Self Refresh modes.
Bank Activate:
BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs:
A0-A12 are sampled during the BankActivate command (row
address A0-A12) and Read/Write command (column address A0-A8 with A10 defining
Auto Precharge).
Chip Select:
CS
enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when
CS
is sampled HIGH.
CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe:
The
RAS
signal defines the operation commands in
conjunction with the
CAS
and
WE
signals and is latched at the positive edges of CK.
When
RAS
and
CS
are asserted "LOW" and
CAS
is asserted "HIGH," either the
BankActivate command or the Precharge command is selected by the
WE
signal.
When the
WE
is asserted "HIGH," the BankActivate command is selected and the
bank designated by BA is turned on to the active state. When the
WE
is asserted
"LOW," the Precharge command is selected and the bank designated by BA is
switched to the idle state after the precharge operation.
Column Address Strobe:
The
CAS
signal defines the operation commands in
conjunction with the
RAS
and
WE
signals and is latched at the positive edges of CK.
When
RAS
is held "HIGH" and
CS
is asserted "LOW," the column access is started
by asserting
CAS
"LOW." Then, the Read or Write command is selected by asserting
WE
"HIGH" or “LOW”.
Write Enable:
The
WE
signal defines the operation commands in conjunction with
the
RAS
and
CAS
signals and is latched at the positive edges of CK. The
WE
input
is used to select the BankActivate or Precharge command and Read or Write
command.
Bidirectional Data Strobe:
Specifies timing for Input and Output data. Read Data
Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data
and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15.
Data Input Mask:
Input data is masked when DM is sampled HIGH during a write
cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
Data I/O:
The DQ0-DQ15 input and output data are synchronized with the positive
edges of CK and
CK
The I/Os are byte-maskable during Writes.
CKE
Input
BA0, BA1
A0-A12
Input
Input
CS
Input
RAS
Input
CAS
Input
WE
Input
LDQS,
UDQS
LDM,
UDM
DQ0 - DQ15
Input /
Output
Input
Input /
Output
Alliance Memory, lnc. Confidential
4
Rev. 1.1
Sep. /2011
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