ispLSI 2096E
In-System Programmable
SuperFAST™ High Density PLD
Features
• SUPERFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional/JEDEC Upward Compatible with
ispLSI 2096 Devices
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 180 MHz Maximum Operating Frequency
—
t
pd
= 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O Supports Mixed-
Voltage Systems
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
®
Functional Block Diagram
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C7
A0
C6
C5
C4
C3
C2
C1
C0
B7
Output Routing Pool (ORP)
D Q
A1
A2
GLB
Logic
Array
D Q
B6
D Q
Global Routing Pool
(GRP)
B5
D Q
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0919/2096E
Description
The ispLSI 2096E is a High Density Programmable Logic
Device. The device contains 96 Registers, 96 Universal
I/O pins, six Dedicated Input pins, three Dedicated Clock
Input pins, two dedicated Global OE input pins and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2096E features 5V in-system programmability
and in-system diagnostic capabilities. The ispLSI 2096E
offers non-volatile reprogrammability of all logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
The basic unit of logic on the ispLSI 2096E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
2096e_04
1
Output Routing Pool (ORP)
Specifications
ispLSI 2096E
Functional Block Diagram
Figure 1. ispLSI 2096E Functional Block Diagram
GOE 0
GOE 1
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
IN 5
IN 4
Input Bus
Input Bus
Output Routing Pool (ORP)
Megablock
Generic Logic
Blocks (GLBs)
C7
Output Routing Pool (ORP)
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP)
Input Bus
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
A1
A2
Global
Routing
Pool
(GRP)
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
A0
B7
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
B6
B5
A3
B4
A4
A5
A6
A7
B0
B1
B2
B3
TDO
RESET
BSCAN
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Input Bus
CLK 0
CLK 1
CLK 2
I/O 44
I/O 45
I/O 46
I/O 47
I/O 36
I/O 37
I/O 38
I/O 39
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
IN 2
TCK/IN 3
I/O 32
I/O 33
I/O 34
I/O 35
I/O 40
I/O 41
I/O 42
I/O 43
0917/2096E
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096E device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.
2
Y0
Y1
Y2
Specifications
ispLSI 2096E
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Supply Voltage: Logic Core, Input Buffers
Supply Voltage: Output Drivers
Input Low Voltage
Input High Voltage
5V
3.3V
T
A
= 0°C to +70°C
MIN.
4.75
4.75
3.0
0
2.0
MAX.
5.25
5.25
3.6
0.8
V
cc
+1
UNITS
V
V
V
V
V
Table 2-0005/2096E
V
CC
V
CCIO
V
IL
V
IH
Capacitance (T
A
=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock Capacitance
TYP
8
8
10
UNITS
pf
pf
pf
TEST CONDITIONS
V
CC
= 5.0V, V
IN
= 2.0V
V
CC
= 5.0V, V
I/O
= 2.0V
V
CC
= 5.0V, V
Y
= 2.0V
Table 2-0006/2096E
C
1
C
2
C
3
Erase/Reprogram Specification
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10,000
MAXIMUM
–
UNITS
Cycles
Table 2-0008/2096E
3
Specifications
ispLSI 2096E
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
1.5 ns
1.5V
1.5V
See Figure 2
Table 2-0003/2128E
Figure 2. Test Load
+ 5V
R1
Device
Output
Test
Point
R2
C L
*
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
*
CL includes Test Fixture and Probe Capacitance.
0213A
C
Table 2 - 0004A/2000
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
(V
CCIO
- 0.2)V
≤
V
IN
≤
V
CCIO
V
CCIO
≤
V
IN
≤
5.25V
0V
≤
V
IN
≤
2.0V
V
CCIO
= 5.0V or 3.3V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V
f
TOGGLE
= 1 MHz
CONDITION
MIN.
–
2.4
–
–
–
-10
–
–
TYP.
3
–
–
–
–
–
–
–
130
MAX. UNITS
0.4
–
-10
10
10
-250
-240
–
V
V
µA
µA
µA
µA
mA
mA
V
OL
V
OH
I
IL
I
IH
I
IL-PU
I
OS
1
I
CC
3,4
Table 2-0007/2096E
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Meaured using six 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Unused inputs held at 0.0V.
5. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I
CC
.
4
Specifications
ispLSI 2096E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
2
4
#
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
DESCRIPTION
1
-180
–
–
180
1
-135
–
–
135
100
143
5.0
–
0.0
6.0
–
0.0
–
5.0
–
–
–
–
3.5
3.5
7.5
10.0
–
–
–
–
4.0
–
–
4.5
–
10.0
–
12.0
12.0
7.0
7.0
–
–
–
–
-100
10.0
13.0
–
–
–
–
5.0
–
–
6.0
–
13.5
–
15.0
15.0
9.0
9.0
–
–
MIN. MAX. MIN. MAX. MIN. MAX.
5.0
7.5
–
–
–
–
3.0
–
–
3.5
–
7.0
–
10.0
10.0
5.0
5.0
–
–
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
1 Data Prop Delay, 4PT Bypass, ORP Bypass
2 Data Prop Delay
3 Clk Freq with Internal Feedback
3
4 Clk Freq with External Feedback
(
tsu2 + tco1
)
5 Clk Frequency, Max. Toggle
6 GLB Reg Setup Time before Clk, 4 PT Bypass
7 GLB Reg Clk to Output Delay, ORP Bypass
8 GLB Reg Hold Time after Clk, 4 PT Bypass
9 GLB Reg Setup Time before Clk
10 GLB Reg Clk to Output Delay
11 GLB Reg Hold Time after Clk
12 External Reset Pin to Output Delay
13 External Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 External Synch Clk Pulse Duration, High
19 External Synch Clk Pulse Duration, Low
100
77
100
6.5
–
0.0
8.0
–
0.0
–
6.5
–
–
–
–
5.0
5.0
125
200
4.0
–
0.0
5.0
–
0.0
–
4.0
–
–
–
–
2.5
2.5
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
Table 2-0030A/2096E
5
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
