Operating Temperature Range ........................... -40NC to +85NC
Junction Temperature ......................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................. +300NC
Soldering Temperature (reflow) .......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics
(Note 1)
µMAX
Junction-to-Ambient Thermal Resistance (q
JA
)........ 113NC/W
Junction-to-Case Thermal Resistance (q
JC
) ..............36NC/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz, V
REF
= 5V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25NC.) (Note 2)
PARAMETER
ANALOG INPUT (Note 3)
Input Voltage Range
Absolute Input Voltage Range
Input Leakage Current
Input Capacitance
Input-Clamp Protection Current
STATIC PERFOMANCE (Note 4)
Resolution
No Missing Codes
Offset Error
Offset Temperature Coefficient
Gain Error
Gain Error Temperature Coefficient
Integral Nonlinearity
Differential Nonlinearity
Positive Full-Scale Error
INL
DNL
-5.5
-0.9
-65
-57
N
18
18
-0.5
-25
±0.1
±5
±1
±8
±0.25
±2
±0.5
+5.5
+0.9
+65
+57
+0.5
+25
Bits
Bits
mV
LSB
µV/°C
LSB
ppm/°C
LSB
LSB
LSB
Both inputs
-20
AIN+ to AIN-
AIN+ to GND
AIN- to GND
Acquisition phase
0
-0.1
-0.1
-10
+0.001
40
+20
V
REF
V
REF
+
0.1
+0.1
+10
µA
pF
mA
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
www.maximintegrated.com
Maxim Integrated
│
2
MAX11152
18-Bit, 500ksps, +5V Unipolar Input, SAR ADC,
in Tiny 10-Pin µMAX
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz, V
REF
= 5V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25NC.) (Note 2)
PARAMETER
Analog Input CMR
Power-Supply Rejection (Note 5)
Transition Noise
REFERENCE (Note 7)
REF Voltage Input Range
REF Input Capacitance
REF Load Current
DYNAMIC PERFOMANCE (Note 6)
Signal-to-Noise Ratio (Note 7)
Signal-to-Noise Plus Distortion
(Note 7)
Spurious-Free Dynamic Range
Total Harmonic Distortion
Intermodulation Distortion (Note 8)
SAMPLING DYNAMICS
Throughput Sample Rate
Transient Response
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
POWER SUPPLIES
Analog Supply Voltage
Interface Supply Voltage
Analog Supply Current
V
DD
Shutdown Current
Interface Supply Current (Note 9)
OVDD Shutdown Current
Power Dissipation
V
DD
= 5V, V
OVDD
= 3.3V
V
OVDD
= 2.3V
V
OVDD
= 5.25V
V
DD
V
OVDD
I
VDD
4.75
2.3
2.8
0.01
1.5
4.1
0.01
23
5.25
5.25
3.8
10
2.0
5.0
10
V
V
mA
µA
mA
µA
mW
Full-scale step
-3dB point
-0.1dB point
6
> 0.2
2.5
10
0
500
400
ksps
ns
MHz
ns
ps
RMS
SNR
SINAD
SFDR
THD
IMD
f
IN
= 10kHz, V
REF
= 5V
f
IN
= 10kHz, V
REF
= 2.5V
f
IN
= 10kHz, V
REF
= 5V
96
95
89
94.7
106
-106
-115
-96
dB
dB
dB
dB
dB
dBFS
V
REF
2.5
20
140
V
DD
V
pF
µA
SYMBOL
CMR
PSR
PSR vs. V
DD
CONDITIONS
MIN
TYP
12.5
14.5
1.65
MAX
UNITS
LSB/V
LSB/V
LSB
RMS
www.maximintegrated.com
Maxim Integrated
│
3
MAX11152
18-Bit, 500ksps, +5V Unipolar Input, SAR ADC,
in Tiny 10-Pin µMAX
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz, V
REF
= 5V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
0.7 x
V
OVDD
0.3 x
V
OVDD
±0.05 x
V
OVDD
10
V
IN
= 0V or V
OVDD
-10
V
OVDD
- 0.4
0.4
-10
15
t
CYC
t
CONV
t
ACQ
t
CNVPW
t
SCLK
CNVST rising to data available
t
ACQ
= t
CYC
- t
CONV
CS
mode
V
OVDD
> 4.5V
SCLK Period (CS Mode)
V
OVDD
> 2.7V
V
OVDD
> 2.3V
V
OVDD
> 4.5V
SCLK Period (Daisy-Chain Mode)
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Valid
Delay
CNVST Low to SDO D15 MSB Valid
(CS Mode)
CNVST High or SDI High or Last
SCLK Falling Edge to SDO High
Impedance
t
SCLK
t
SCLKL
t
SCLKH
V
OVDD
> 4.5V
t
DSDO
V
OVDD
> 2.7V
V
OVDD
> 2.3V
t
EN
t
DIS
V
OVDD
> 2.7V
V
OVDD
< 2.7V
CS
mode
V
OVDD
> 2.7V
V
OVDD
> 2.3V
2
1.3
0.5
5
14
20
25
16
24
30
6
6
12
18
23
14
18
20
ns
ns
ns
ns
ns
ns
1.5
+10
+10
TYP
MAX
UNITS
DIGITAL INPUTS (SDI, SCLK, CNVST)
Input Voltage High
Input Voltage Low
Input Hysteresis
Input Capacitance
Input Current
DIGITAL OUTPUT (SDO)
Output Voltage High
Output Voltage Low
Three-State Leakage Current
Three-State Output Capacitance
TIMING (Note 9)
Time Between Conversions
Conversion Time
Acquisition Time
CNVST Pulse Width
µs
µs
µs
ns
V
OH
V
OL
I
SOURCE
= 2mA
I
SINK
= 2mA
V
V
µA
pF
V
IH
V
IL
V
HYS
C
IN
I
IN
V
V
V
pF
µA
ns
www.maximintegrated.com
Maxim Integrated
│
4
MAX11152
18-Bit, 500ksps, +5V Unipolar Input, SAR ADC,
in Tiny 10-Pin µMAX
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz, V
REF
= 5V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25NC.) (Note 2)
PARAMETER
SDI Valid Setup Time from CNVST
Rising Edge
SDI Valid Hold Time from SCLK
Rising Edge
SYMBOL
t
SSDISCK
t
HSDISCK
CONDITIONS
4-wire
CS
mode
4-wire
CS
mode
Daisy-chain mode
MIN
5
0
5
5
6
0
15
20
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
SCLK Valid Setup Time from CNVST
t
SSCKCNV
Rising Edge
SCLK Valid Hold Time from CNVST
Rising Edge
SDI Valid Setup Time from SCLK
Falling Edge
SDI Valid Hold Time from SCLK
Falling Edge
t
HSCKCNV
Daisy-chain mode
t
SSDISCK
t
HSDISCK
Daisy-chain mode
Daisy-chain mode
Daisy-chain mode with busy indicator,
V
OVDD
> 4.5V
V
OVDD
> 2.3V
SDI High to SDO High
t
DSDOSDI
ns
Note 2:
Maximum and minimum limits are fully production tested over the specified supply voltage range and at a temperature of
+25°C and +85°C. Limits below +25°C are guaranteed by design and device characterization.
Note 3:
See the
Analog Inputs
and
Overvoltage Input Clamps
sections.
Note 4:
See the
Definitions
section.
Note 5:
Defined as the change in positive full-scale code transition caused by a
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
