19-2362; Rev 1; 3/02
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
General Description
The MAX3875A is a compact, low-power clock recov-
ery and data retiming IC for 2.488Gbps SDH/SONET
applications. The fully integrated phase-locked loop
recovers a synchronous clock signal from the serial
NRZ data input, which is retimed by the recovered
clock. Differential PECL-compatible outputs are provid-
ed for both clock and data signals, and an additional
2.488Gbps serial input is available for system loopback
diagnostic testing. The device also includes a TTL-
compatible loss-of-lock (LOL) monitor.
The MAX3875A is designed for both section-regenerator
and terminal-receiver applications in OC-48/STM-16
transmission systems. Its jitter performance exceeds all
of the SONET/SDH specifications.
This device operates from a single +3.3V to +5.0V supply
over a -40°C to +85°C temperature range. The typical
power consumption is only 400mW with a +3.3V supply. It is
available in a 32-pin TQFP package, as well as in die form.
Features
o
Exceeds ANSI, ITU, and Bellcore SONET/SDH
Regenerator Specifications
o
400mW Power Dissipation (at +3.3V)
o
Clock Jitter Generation: 0.003UI
RMS
o
Single +3.3V or +5V Power Supply
o
Fully Integrated Clock Recovery and Data Retiming
o
Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
o
Tolerates >2000 Consecutive Identical Digits
o
Loss-of-Lock Indicator
o
Differential PECL-Compatible Data and Clock
Outputs
MAX3875A
Ordering Information
PART
MAX3875AEHJ
MAX3875AE/D
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Dice*
Applications
SDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
2.488Gbps ATM Receiver
Digital Video Transmission
SDH/SONET Test Equipment
*
Dice are designed to operate over this range, but are tested
and guaranteed at T
A
= +25°C only. Contact factory for
availability.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
+3.3V
PHOTO-
DIODE
V
CC
0.01µF
0.01µF
V
CC
PHADJ+ PHADJ- LOL
SDO+
SDO-
82Ω
SDI-
SLBI-
SLBI+
SIS
FIL+
FIL-
SCLKO+
SCLKO-
82Ω
82Ω
82Ω
+3.3V
MAX3885
130Ω
130Ω
1:16
DESERIALIZER
130Ω
130Ω
TTL
+3.3V
+3.3V
MAX3866
IN
OUT+
SDI+
PRE/POSTAMPLIFIER
LOP
TTL
OUT-
MAX3875A
SYSTEM
LOOPBACK
TTL
1µF
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
MAX3875A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
..............................................-0.5V to +7.0V
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-) ...........(V
CC
- 0.5V) to (V
CC
+ 0.5V)
Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±10mA
PECL Output Voltage
(SDO+, SDO-, SCLKO+, SCLKO-) .......................(V
CC
+ 0.5V)
PECL Output Current, (SDO+, SDO-, SCLKO+, SCLKO-).....56mA
Voltage at
LOL,
SIS, PHADJ+, PHADJ-,
FIL+, FIL- .................................................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
TQFP (derate 16.1mW/°C above +85°C) ........................1.0W
Operating Temperature Range
MAX3875EHJ..................................................-40°C to +85°C
Operating Junction Temperature (die) ..............-55°C to +150°C
Storage Temperature Range .............................-60°C to +160°C
Processing Temperature (die) .........................................+400°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +5.5V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and T
A
= +25°C.) (Note 1)
PARAMETER
Supply Current
Differential Input Voltage
(SDI±, SLBI±)
Single-Ended Input Voltage
(SDI±, SLBI±)
Input Termination to V
CC
(SDI±, SLBI±)
PECL Output High Voltage
(SDO±, SCLKO±)
PECL Output Low Voltage
(SDO±, SCLKO±)
TTL Input High Voltage (SIS)
TTL Input Low Voltage (SIS)
TTL Input Current (SIS)
TTL Output High Voltage (LOL)
TTL Output Low Voltage (LOL)
V
OH
V
OL
SYMBOL
I
CC
V
ID
V
IS
R
IN
V
OH
V
OL
V
IH
V
IL
-10
2.4
T
A
= 0°C to +85°C
T
A
= -40°C
T
A
= 0°C to +85°C
T
A
= -40°C
V
CC
- 1.025
V
CC
- 1.085
V
CC
- 1.81
V
CC
- 1.83
2.0
0.8
+10
V
CC
0.4
CONDITIONS
Excluding PECL output termination
Figure 1
50
V
CC
- 0.4
45
V
CC
- 0.88
V
CC
- 0.88
V
CC
- 1.62
V
CC
- 1.555
MIN
TYP
122
MAX
167
800
V
CC
+ 0.2
UNITS
mA
mV
P-P
V
Ω
V
V
V
V
µA
V
V
Note 1:
Dice are tested at T
A
= +25°C only.
t
CK
SDI+
SDI-
25mV MIN
400mV MAX
SCLKO+
t
CK-Q
SDO
(SDI+) -
(SDI-)
V
ID
50mV
P-P
MIN
800mV
P-P
MAX
Figure 1. Input Amplitude
2
Figure 2. Output Clock-to-Q Delay
_______________________________________________________________________________________
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +5.5V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and T
A
= +25°C.) (Note 2)
PARAMETER
Serial Output Clock Rate
Clock-to-Q Delay
Jitter Peaking
Jitter Transfer Bandwidth
J
P
J
BW
f = 70kHz
Jitter Tolerance
f = 100kHz
f = 1MHz
f = 10MHz (Note 3)
Jitter Generation
Clock Output Edge Speed
Data Output Edge Speed
Tolerated Consecutive
Identical Digits
Input Return Loss
(SDI±, SLBI±)
100kHz to 2.5GHz
2.5GHz to 4.0GHz
J
GEN
Jitter BW = 12kHz to 20MHz
20% to 80%
20% to 80%
1.91
1.76
0.41
0.21
Figure 2
f
≤
2MHz
1.1
3.6
2.75
0.67
0.45
0.003
0.026
70
108
2000
-17
-15
0.006
0.056
UI
RMS
UI
P-P
ps
ps
bits
dB
UI
P-P
110
SYMBOL
CONDITIONS
MIN
TYP
2.488
290
0.1
2.0
MAX
UNITS
Gbps
ps
dB
MHz
MAX3875A
Note 2:
AC characteristics are guaranteed by design and characterization.
Note 3:
See
Typical Operating Characteristics
for worst-case distribution.
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
RECOVERED DATA AND CLOCK
(DIFFERENTIAL OUTPUT)
MAX3875A toc01
RECOVERED CLOCK JITTER
PRBS = 2
15
- 1
MAX3875A toc02
JITTER TOLERANCE
MAX3875A toc03
10
INPUT JITTER (UI
P-P
)
2
23
- 1 PATTERN
V
IN
= 20mV
P-P
T
A
= +85°C
DATA
1
BELLCORE
MASK
CLOCK
RMS∆ = 1.2ps
0.1
100ps/div
10ps/div
PRBS = 2
23
- 1
50mV
P-P
INPUT
10k
100k
1M
10M
JITTER FREQUENCY (Hz)
_______________________________________________________________________________________
3
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
MAX3875A
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
JITTER TOLERANCE vs. INPUT VOLTAGE
MAX3875A toc04
DISTRIBUTION OF JITTER TOLERANCE
MAX3875A toc05a
JITTER TRANSFER
0
-0.3
JITTER TRANSFER (dB)
-0.6
-0.9
-1.2
-1.5
-1.8
-2.1
-2.4
-2.7
PRBS = 2
23
- 1
1k
10k
100k
1M
10M
-3.0
BELLCORE
MASK
MAX3875A toc05
0.8
0.7
JITTER TOLERANCE (UI
P-P
)
0.6
0.5
0.4
0.3
0.2
JITTER FREQUENCY
= 5MHz
JITTER FREQUENCY
= 1MHz
30
25
PERCENT OF UNITS (%)
20
15
10
5
MEAN = 0.41
σ
= 0.028
f
JITTER
= 10MHz
V
CC
= +3.0V
T
A
= -40°C
0.3
0.1
0
1
PRBS = 2
23
- 1
0
10
100
1000
0.20
0.34
0.48
0.62
INPUT VOLTAGE (mV
P-P
)
JITTER TOLERANCE (UI
P-P
)
JITTER FREQUENCY (Hz)
BIT ERROR RATE vs. INPUT VOLTAGE
MAX3875A toc06
SUPPLY CURRENT
vs. TEMPERATURE
140
SUPPLY CURRENT (mA)
135
130
125
V
CC
= +3.3V
120
115
V
CC
= +5.0V
MAX3875A toc07
10
-3
10
-4
10
-5
BIT ERROR RATE
10
-6
10
-7
10
-8
10
-9
PRBS = 2
23
- 1
10
-10
6.0
6.1
6.2
6.3
6.4
6.5
145
110
105
6.6
-50
-25
0
25
50
75
100
INPUT VOLTAGE (mV
P-P
)
AMBIENT TEMPERATURE (°C)
Pin Description
PIN
1, 2, 8, 9,
10, 16, 26,
29, 32
3, 6, 11,
14, 15, 17,
20, 21, 24
4
5
7
12
13
18
NAME
GND
Supply Ground
FUNCTION
V
CC
SDI+
SDI-
SIS
SLBI+
SLBI-
SCLKO-
Positive Supply Voltage
Positive Data Input. 2.488Gbps serial data stream.
Negative Data Input. 2.488Gbps serial data stream.
Signal Input Selection, TTL. Low for normal data input. High for system loopback input.
Positive System Loopback Input. 2.488Gbps serial data stream.
Negative System Loopback Input. 2.488Gbps serial data stream.
Negative Serial Clock Output, PECL, 2.488GHz. SDO- is clocked out on the falling edge of SCLKO-.
4
_______________________________________________________________________________________
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
Pin Description (continued)
PIN
19
22
23
25
27
28
30
31
NAME
SCLKO+
SDO-
SDO+
LOL
PHADJ-
PHADJ
+
FIL-
FIL+
FUNCTION
Positive Serial Clock Output, PECL, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.
Negative Data Output, PECL compatible, 2.488Gbps
Positive Data Output, PECL compatible, 2.488Gbps
Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩ pull-up resistor)
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not used.
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not used.
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
MAX3875A
SIS
PHADJ+ PHADJ-
FIL+
FIL-
SDO+
SDI+
AMP
SDI-
MUX
SLBI+
AMP
SLBI-
LOL
TTL
PHASE AND
FREQUENCY
DETECTOR
LOOP
FILTER
I
VCO
Q
CML
SCLKO+
SCLKO-
D
CK
Q
CML
SDO-
MAX3875A
Figure 3. Functional Diagram
Detailed Description
The MAX3875A consists of a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
and PECL output buffer (Figure 3). The PLL consists of
a phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
800mV
P-P
. The bit error rate is better than 1 x 10
-10
for
input signals as small as 10mVp-p, although the jitter
tolerance performance will be degraded. For interfacing
with PECL signal levels, see
Applications Information.
Phase Detector
The phase detector incorporated in the MAX3875A pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming. The
external phase adjust pins (PHADJ+, PHADJ-) allow the
user to vary the internal phase alignment.
Input Amplifier
Input amplifiers are implemented for both the main data
and system loopback inputs. These amplifiers accept a
differential input amplitude from 50mV
P-P
up to
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5
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