STL3NK40
N-channel 400 V, 4.5 Ω typ., 0.43 A, SuperMESH™
Power MOSFET in a PowerFLAT™ 5x5 package
Datasheet - production data
Features
Order code
STL3NK40
V
DS
400 V
R
DS(on)
max.
5.5 Ω
I
D
0.43 A
P
TOT
2.5 W
Figure 1: Internal schematic diagram
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Applications
Switching applications
Description
This high voltage device is an N-channel Power
MOSFET developed using the SuperMESH™
technology by STMicroelectronics, an
optimization of the well-established
PowerMESH™. In addition to a significant
reduction in on-resistance, this device is
designed to ensure a high level of dv/dt capability
for the most demanding applications.
Table 1: Device summary
Order code
STL3NK40
Marking
3NK40
Package
PowerFLAT™ 5x5
Packing
Tape and reel
February 2017
DocID16246 Rev 3
1/13
www.st.com
This is information on a product in full production.
Contents
STL3NK40
Contents
1
2
3
4
5
Electrical ratings ............................................................................. 3
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
Test circuits ..................................................................................... 8
Package information ....................................................................... 9
4.1
PowerFLAT™ 5x5 package information .......................................... 10
Revision history ............................................................................ 12
2/13
DocID16246 Rev 3
STL3NK40
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
V
DS
V
DGR
V
GS
I
D
(1)
I
DM
(2)
P
TOT
(1)
dv/dt
(3)
T
j
T
stg
Notes:
(1)
When
(2)
Pulse
(3)
I
SD
Parameter
Drain-source voltage
Drain-gate voltage (R
GS
= 20 kΩ)
Gate-source voltage
Drain current (continuous) at T
pcb
= 25 °C
Drain current (continuous) at T
pcb
= 100 °C
Drain current (pulsed)
Total dissipation at T
pcb
= 25 °C
Peak diode recovery voltage slope
Operating junction temperature range
Storage temperature range
Value
400
400
± 20
0.43
0.27
1.72
2.5
4.5
- 55 to 150
Unit
V
V
V
A
A
A
W
V/ns
°C
mounted on FR-4 board of 1 inch², 2 oz Cu (t < 100 s).
width limited by safe operating area.
≤ 0.43 A, di/dt ≤ 200 A/μs; V
DD
< 320 V.
Table 3: Thermal data
Symbol
R
thj-pcb
(1)
Notes:
(1)
When
Parameter
Thermal resistance junction-pcb
Value
50
Unit
°C/W
mounted on 1 inch² FR-4 board, 2 oz Cu (t < 100 s).
Table 4: Avalanche characteristics
Symbol
I
AR
E
AS
Parameter
Avalanche current, repetitive or non-repetitive (pulse
width limited by T
jmax.
)
Single pulse avalanche energy (starting T
j
= 25 °C,
I
D
= I
AR
, V
DD
= 50 V)
Value
0.43
60
Unit
A
mJ
DocID16246 Rev 3
3/13
Electrical characteristics
STL3NK40
2
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 5: On/off-state
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Notes:
(1)
Defined
Parameter
Drain-source breakdown voltage
Zero-gate voltage drain current
Gate body leakage current
Gate threshold voltage
Static drain-source on-resistance
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 400 V
V
GS
= 0 V, V
DS
= 400 V
T
C
= 125 °C
(1)
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 50 µA
V
GS
= 10 V, I
D
= 0.22 A
Min.
400
Typ.
Max.
Unit
V
1
50
±10
0.8
1.6
4.5
2
5.5
µA
µA
µA
V
Ω
by design, not subject to production test.
Table 6: Dynamic
Symbol
C
iss
C
oss
C
rss
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
f = 1 MHz gate
DC bias = 0 test signal
level = 20 mV open-
drain
V
DD
= 320 V, I
D
= 1.4 A
V
GS
= 0 to 10 V
(see
Figure 13: "Test
circuit for gate charge
behavior")
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
Test conditions
Min.
-
-
-
Typ.
128
16
4
Max.
200
30
6
Unit
pF
pF
pF
R
G
Gate input resistance
-
12
pF
Q
g
Q
gs
Q
gd
Total gate charge
Gate-source charge
Gate-drain charge
-
-
-
8.7
0.9
3.8
13
-
-
nC
nC
nC
Table 7: Switching times
Symbol
t
d(on)
t
r
t
d(off)
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Test conditions
V
DD
= 200 V, I
D
= 0.7 A,
R
G
= 4.7 Ω
V
GS
= 10 V
(see
Figure 12: "Test
circuit for resistive load
switching times"
and
Figure 17: "Switching
time waveform")
Min.
-
-
-
Typ.
3
4
18
Max.
-
-
-
Unit
ns
ns
ns
t
f
Fall time
-
16
-
ns
4/13
DocID16246 Rev 3
STL3NK40
Table 8: Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Notes:
(1)
Pulse
Electrical characteristics
Parameter
Source-drain
current
Source-drain
current (pulsed)
Forward on
voltage
Reverse recovery
time
Reverse recovery
charge
Reverse recovery
current
Reverse recovery
time
Reverse recovery
charge
Reverse recovery
current
I
SD
= 0.43 A, V
GS
= 0 V
Test conditions
Min.
-
-
-
-
I
SD
= 1.4 A, di/dt = 100 A/µs,V
DD
= 20 V
(see
Figure 14: "Test circuit for
inductive load switching and diode
recovery times")
-
-
-
-
-
166
300
3.6
176
340
3.8
Typ.
Max.
0.43
1.72
1.2
Unit
A
A
V
ns
nC
A
ns
nC
A
I
SD
= 1.4 A, di/dt = 100 A/µs V
DD
= 20 V,
T
j
= 150 °C
(see
Figure 14: "Test circuit for
inductive load switching and diode
recovery times")
width limited by safe operating area.
pulse duration = 300 µs, duty cycle 1.5%.
(2)
Pulsed:
DocID16246 Rev 3
5/13
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