STB5N80K5
N-channel 800 V, 1.50 Ω typ., 4 A MDmesh™ K5
Power MOSFET in a D²PAK package
Datasheet - production data
Features
TAB
Order code
STB5N80K5
2
3
1
V
DS
800 V
R
DS(on)
max.
1.75 Ω
I
D
4A
D²PAK
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Applications
Figure 1: Internal schematic diagram
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5
technology based on an innovative proprietary
vertical structure. The result is a dramatic
reduction in on-resistance and ultra-low gate
charge for applications requiring superior power
density and high efficiency.
Table 1: Device summary
Order code
STB5N80K5
Marking
5N80K5
Package
D²PAK
Packing
Tape and reel
May 2016
DocID028512 Rev 2
1/15
www.st.com
This is information on a product in full production.
Contents
STB5N80K5
Contents
1
2
3
4
Electrical ratings ............................................................................. 3
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
Test circuits ..................................................................................... 8
Package information ....................................................................... 9
4.1
4.2
D²PAK (TO-263) type A package information ................................... 9
Packing information......................................................................... 12
5
Revision history ............................................................................ 14
2/15
DocID028512 Rev 2
STB5N80K5
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
V
GS
I
D
I
D
I
D
(1)
P
TOT
dv/dt
(2)
dv/dt
(3)
T
j
T
stg
Notes:
(1)
Pulse
(2)
I
SD
Parameter
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature range
Storage temperature range
Value
± 30
4
2.3
16
60
4.5
50
- 55 to 150
Unit
V
A
A
A
W
V/ns
°C
width limited by safe operating area
≤ 4 A, di/dt =100 A/μs; V
DS
peak < V
(BR)DSS
, V
DD
=640 V
≤ 640 V
(3)
V
DS
Table 3: Thermal data
Symbol
R
thj-case
R
thj-pcb
(1)
Notes:
(1)
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
Value
2.08
35
Unit
°C/W
°C/W
When mounted on FR-4 board of 1 inch², 2 oz Cu
Table 4: Avalanche characteristics
Symbol
I
AR
E
AS
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by
Tjmax)
Single pulse avalanche energy (starting Tj = 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
1.2
165
Unit
A
mJ
DocID028512 Rev 2
3/15
Electrical characteristics
STB5N80K5
2
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 5: On/off-state
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Notes:
(1)
Defined
Parameter
Drain-source breakdown voltage
Zero gate voltage drain current
Gate body leakage current
Gate threshold voltage
Static drain-source on-resistance
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 800 V
V
GS
= 0 V, V
DS
= 800 V
T
C
= 125 °C
(1)
V
DS
= 0 V, V
GS
= ±20 V
V
DD
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 2 A
Min.
800
Typ.
Max.
Unit
V
1
50
±10
3
4
1.50
5
1.75
µA
µA
µA
V
Ω
by design, not subject to production test.
Table 6: Dynamic
Symbol
C
iss
C
oss
C
rss
C
o(tr)
(1)
C
o(er)
(2)
R
g
Q
g
Q
gs
Q
gd
Notes:
(1)
C
o(tr)
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time
related
Equivalent capacitance
energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
Min.
-
-
-
-
Typ.
177
15
0.3
33
12
Max.
-
-
-
-
Unit
pF
pF
pF
pF
pF
V
GS
= 0, V
DS
= 0 to 640 V
f = 1 MHz , I
D
= 0 A
V
DD
= 640 V, I
D
= 4 A
V
GS
= 10 V
(see
Figure 15: "Test circuit
for gate charge behavior")
-
-
-
-
16
5
1.7
2.9
-
-
-
-
Ω
nC
nC
nC
is a constant capacitance value that gives the same charging time as C
oss
while V
DS
is rising from 0 to
80% V
DSS
.
(2)
C
o(er)
is a constant capacitance value that gives the same stored energy as C
oss
while V
DS
is rising from 0 to
80% V
DSS
.
4/15
DocID028512 Rev 2
STB5N80K5
Table 7: Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
V
DD
= 400 V, I
D
= 2 A, R
G
= 4.7 Ω
V
GS
= 10 V
(see
Figure 14: "Test circuit for
resistive load switching times"
and
Figure 19: "Switching time
waveform")
Electrical characteristics
Min.
-
-
-
-
Typ.
12.7
11.7
23
14.8
Max.
-
-
-
-
Unit
ns
ns
ns
ns
Table 8: Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Notes:
(1)
Pulse
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
Min.
-
-
Typ.
Max.
4
16
1.5
Unit
A
A
V
ns
µC
A
ns
µC
A
I
SD
= 4 A, V
GS
= 0 V
I
SD
= 4 A, di/dt = 100
A/µs,V
DD
= 60 V
(see
Figure 16: "Test circuit
for inductive load switching
and diode recovery times")
I
SD
= 4 A, di/dt = 100 A/µs
V
DD
= 60 V, T
j
= 150 °C
(see
Figure 16: "Test circuit
for inductive load switching
and diode recovery times")
-
-
-
-
-
-
-
265
1.59
12
386
2.18
11.3
width limited by safe operating area
pulse duration = 300 µs, duty cycle 1.5%
(2)
Pulsed:
Table 9: Gate-source Zener diode
Symbol
V
(BR)GSO
Parameter
Gate-source breakdown voltage
Test conditions
I
GS
= ± 1mA, I
D
= 0 A
Min.
30
Typ.
-
Max.
-
Unit
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD
performance of the device. The Zener voltage facilitates efficient and cost-effective device
integrity protection, thus eliminating the need for additional external componentry.
DocID028512 Rev 2
5/15
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