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isp22v10a_03.0
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
ispGAL Architecture
Output Logic Macrocell (OLMC)
The ispGAL22V10A has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs
have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve
product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen
product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional
product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or
registered mode. This allows each output to be individually configured as either active high or active low.
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Figure 2. Output Logic Macrocell
AR
D
Q
The ispGAL22V10A has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset
(SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to
zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on
the rising edge of the next clock pulse after this product term is asserted.
NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the
polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a
high or low at the output pin, depending on the pin polarity chosen.
4 TO 1
MUX
CLK
Q
SP
2 TO 1
MUX
Output Logic Macrocell Configurations
Each of the Macrocells of the ispGAL22V10A has two primary functional modes: registered, and combinatorial I/O.
The modes and the output polarity are set by two bits (S0 and S1), which are normally controlled by the logic com-
piler. Each of these two primary modes, and the bit settings required to enable them, are described below and on
the following page.
Registered
In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-
type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive
either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for
each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND
array, with both the true and complement of the feedback available as inputs to the AND array.
2
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin
defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins.
Combinatorial I/O
In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate.
Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true
(active high) or inverted (active low). Output tri-state control is available as an individual product-term for each out-
put, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “prod-
uct-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both
polarities (true and inverted) of the pin are fed back into the AND array.
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