HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
Features
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IDT70V07S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 25/35ns (max.)
Low-power operation
– IDT70V07S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V07L
Active: 300mW (typ.)
Standby: 660
µ
W (typ.)
Interrupt Flag
IDT70V07 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 80-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
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Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1,2)
I/O
Control
I/O
0R
-I/O
7R
,
BUSY
R
Address
Decoder
15
(1,2)
A
14L
A
0L
MEMORY
ARRAY
15
Address
Decoder
A
14R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R(2)
2943 drw 01
MARCH 2018
1
DSC 2943/10
©2018 Integrated Device Technology, Inc.
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The
IDT70V07 is designed to be used as a stand-alone 256K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-
or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 16-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices
typically operate on only 300mW of power.
The IDT70V07 is packaged in a ceramic 68-pin PGA and PLCC and
a 80-pin thin quad flatpack (TQFP).
Pin Configurations
(1,2,3)
10/25/01
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
1L
I/O
0L
N/C
OE
L
R/W
L
SEM
L
CE
L
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
IDT70V07J
J68-1
(4)
68-Pin PLCC
Top View
(5)
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
2943 drw 02
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
7R
N/C
OE
R
R/W
R
SEM
R
CE
R
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
2
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
10/25/01
INDEX
N/C
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
N/C
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
53
8
IDT70V07PF
(4)
9
PN80-1
52
10
51
11
50
12
49
80-Pin TQFP
(5)
13
48
Top View
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
I/O
1L
I/O
0L
N/C
OE
L
R/W
L
SEM
L
CE
L
N/C
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
2943 drw 03
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
7R
N/C
OE
R
R/W
R
SEM
R
CE
R
N/C
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
N/C
N/C
3
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
10/25/01
51
11
53
A
7L
55
A
9L
A
5L
52
A
6L
54
A
8L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/S
40
38
R
A
1R
INT
36
A
3R
35
A
4R
32
A
7R
30
A
9R
34
A
5R
33
A
6R
31
A
8R
29
A
10R
27
A
12R
10
45
43
41
39
37
INT
L
GND
BUSY
R
A
0R
A
2R
09
08
57
56
A
11L
A
10L
59
58
V
CC
A
12L
61
60
A
13L
07
IDT70V07G
G68-1
(4)
68-Pin PGA
Top View
(5)
28
A
11R
26
GND
06
A
14L
05
63
62
SEM
L
CE
L
65
64
OE
L
R/W
L
67
66
I/O
0L
N/C
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
4
I/O
3L
I/O
5L
B
C
24
25
A
14R
A
13R
22
23
SEM
R
CE
R
20
OE
R
21
R/W
R
04
03
02
5
7
9
11
13
15
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
6
I/O
6L
D
8
10
12
14
16
V
CC
I/O
0R
I/O
2R
I/O
3R
I/O
5R
E
F
G
H
J
18
19
I/O
7R
N/C
17
I/O
6R
K
,
01
A
INDEX
L
2943 drw 04
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
14L
I/O
0L
- I/O
7L
SEM
L
INT
L
BUSY
L
Right Port
CE
R
R/W
R
OE
R
A
0R
- A
14R
I/O
0R
- I/O
7R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power (3.3V)
Ground (0V)
2943 tbl 01
4
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
2943 tbl 02
Mode
NOTE:
1. A
0L
— A
14L
≠
A
0R
— A
14R
Truth Table II: Semaphore Read/Write Control
Inputs
(1)
CE
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-7
DATA
OUT
DATA
IN
____
Mode
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
2943 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
7
). These eight semaphores are addressed by A
0
-A
2
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to GND
Temperature Under Bias
StorageTemperature
Junction Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +4.6
-55 to +125
-65 to +150
+150
50
Unit
V
o
o
o
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Industrial
Ambient Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V
+
0.3
3.3V
+
0.3
2943 tbl 05
T
BIAS
(3)
T
STG
T
JN
I
OUT
C
C
C
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
mA
2943 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Recommended DC Operating
Conditions
(2)
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
CC
+0.3
(2)
0.8
Unit
V
V
V
V
2943 tbl 06
Capacitance
(1)
Symbol
C
IN
C
OUT
(2)
Input Capacitance
(T
A
= +25°C, f = 1.0MHz) TQFP Only
Parameter
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
9
10
Unit
pF
pF
2943 tbl 07
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.3V.
Output Capacitance
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. C
OUT
also references C
I/O
.
5
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