Low Skew, 1-to-4
Differential-to-3.3V LVPECL Fanout Buffer
G
ENERAL
D
ESCRIPTION
The 8533I-01 is a low skew, high performance 1-to-4
Differential-to-3.3V LVPECL Fanout Buffer. The 8533I-01 has
two selectable clock inputs. The CLK, nCLK pair can accept
most standard differential input levels. The PCLK, nPCLK pair
can accept LVPECL, CML, or SSTL input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the 8533I-01 ideal for those applications demanding well defined
performance and repeatability.
8533I-01
DATA SHEET
F
EATURES
•
Four differential 3.3V LVPECL outputs
•
Selectable differential CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
Maximum output frequency: 650MHz
•
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 150ps (maximum)
•
Propagation delay: 1.5ns (maximum), CLK/nCLK
•
Additive phase jitter, RMS: 0.060ps (typical)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
8533I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
8533I-01 REVISION A 7/9/15
1
©2015 Integrated Device Technology, Inc.
8533I-01 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8, 9
10, 13, 18
11, 12
14, 15
16, 17
19, 20
Name
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
V
CC
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Input
Input
Input
Unused
Power
Output
Output
Output
Output
Pullup
Type
Description
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high. LVC-
MOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential PCLK, nPCLK inputs.
Pulldown
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup
Pullup
Inverting differential clock input.
Inverting differential LVPECL clock input.
No connect.
Positive supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Pulldown Non-inverting differential LVPECL clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
2
REVISION A 7/9/15
8533I-01 DATA SHEET
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Outputs
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs
as described
in Table 3B.
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK or nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ3
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
REVISION A 7/9/15
3
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
8533I-01 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
52
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
0.15
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4
REVISION A 7/9/15
8533I-01 DATA SHEET
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input High Current
Input Low Current
PCLK
nPCLK
PCLK
nPCLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.3
V
EE
+ 1.5
V
CC
- 1.4
V
CC
- 2.0
0.6
1
V
CC
V
CC
- 0.9
V
CC
- 1.7
1.0
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
V
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Peak-to-Peak Output Voltage Swing
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50Ω to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay;
NOTE 1
CLK, nCLK
PCLK, nPCLK
1.15
1.0
Test Conditions
Minimum
Typical
Maximum
650
1.5
1.3
30
150
0.060
300
47
800
53
Units
MHz
ns
ns
ps
ps
ps
ps
%
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
Output Duty Cycle
All parameters measured at f £ 650MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
REVISION A 7/9/15
5
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
实时操作系统RTOS
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