AS4C32M32MD1
Revision History AS4C32M32MD1 - 90-ball FBGA PACKAGE
Revision
Rev 1.0
Details
Preliminary datasheet
Date
September 2014
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
-1-
Rev.1.0
Sep.2014
AS4C32M32MD1
32M x 32 bit MOBILE DDR Synchronous DRAM (SDRAM)
Confidential
Feature
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Advanced (Rev. 1.0, Sep. /2014)
Description
The AS4C32M32MD1 is a four bank mobile
DDR DRAM organized as 4 banks x 8M x 32. It
achieves high speed data transfer rates by
employing a chip architecture that pre-fetches
multiple bits and then synchronizes the output data
to a system clock.
All of the controls, address, circuits are
synchronized with the positive edge of an
externally sup-plied clock. I/O transactions are
possible on both edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with
standard DRAMs. A sequential and gapless data
rate is possible depending on burst length, CAS
latency and speed grade of the device.
Additionally, the device supports low power
saving features like PASR, Auto-TCSR, DPD as
well as options for different drive strength. It’s
ideally suit-able for mobile application.
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4 banks x 8M x 32 organization
Data Mask for Write Control (DM)
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8, 16 for Sequential Type
2, 4, 8, 16 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64ms
Available in 90-ball BGA
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input
and output data, active on both edges
Differential clock inputs CLK and /CLK
Power Supply 1.7V - 1.95V
Drive Strength (DS) Option:Full, 1/2, 1/4, 3/4
Auto Temperature-Compensated Self Refresh
(Auto TCSR)
Partial-Array Self Refresh (PASR) Option: Full,
1/2, 1/4, 1/8, 1/16
Deep Power Down (DPD) mode
Operating Temperature Range
- Commercial -25°C to 85°C
(Extended)
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Industrial -40°C to 85°C
Table 1. Speed Grade Information
Speed Grade – Data rate Clock Frequency
400Mbps (max)
200 MHz (max)
CAS Latency
3
t
RCD
(ns)
15
t
RP
(ns)
15
Table 2 – Ordering Information for ROHS Compliant Products
Product part No
AS4C32M32MD1-5BCN
AS4C32M32MD1-5BIN
Org
32M x 32
32M x 32
Temperature
Package
Commercial -
25°C
to
85°C
90-ball BGA
(Extended)
Industrial -40°C to 85°C
90-ball BGA
Confidential
-2-
Rev.1.0
Sep.2014
AS4C32M32MD1
Block Diagram (32M
x 32)
Column Addresses
*
A0-A9 (A0-A8), AP, BA0, BA1
Row Addresses *
Reduced Page size
A0-A12 (A0-A13)*, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank B
Row decoder
Memory array
Bank C
Row decoder
Memory array
Bank D
Bank A
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
8192 x 1024
x32 bits
8192 x 1024
x32 bits
8192 x 1024
x32 bits
8192 x 1024
x32 bits
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
31
CKE
RAS
CAS
WE
CS
CLK, CLK
Strobe
Gen.
Data Strobe
DM0 - DM3
CLK
CLK
DQS0 - DQS3
Confidential
-3-
Rev.1.0
Sep.2014
AS4C32M32MD1
32MX32 90 BALL BGA
CONFIGURATION
9
A
B
C
D
E
F
G
H
J
K
8
7
6
5
Top View
Pin Names
CLK, CLK
CKE
CS
RAS
CAS
WE
DQS0, DQS1,
DQS2, DQS3
A
0
–A
13
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
BA0, BA1
DQ
0
–DQ
31
DM0, DM1, DM3,
DM3
V
DD
V
SS
V
DDQ
V
SSQ
NC
Bank Select
Data Input/Output
Data Mask
Power (1.7V - 1.95V)
Ground
Power for I/O’s (1.7V - 1.95V)
Ground for I/O’s
No Connect
Confidential
-4-
Rev.1.0
Sep.2014
AS4C32M32MD1
Signal Pin Description
Pin
CLK
CLK
CKE
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CLK.
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
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During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
and A0-A13 defines the row address (RA0-RA13) for 32Mx32 reduced page size when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
and A0-A8 defines tthe column address (CA0-CA8) for 32Mx32 reduced page size when
sampled at the rising clock edge.
In addition to the column address, A10 is used to invoke autoprecharge operation at the
end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0,
BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
CS
Input
Pulse
RAS, CAS
WE
A0 - A13
Input
Pulse
Input
Level
DQx
Input/
Output
Input
Level
Data Input/Output pins operate in the same manner as conventional DRAMs.
BA0,
BA1
LDQS,
UDQS
(DQS0~3)
Level
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Selects which bank is to be active.
Input/
Output
Level
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Data Input/Output are synchronous edges of the DQS. LDQS for DQ0-DQ7, UDQS for
DQ8-DQ15 in 32Mx16. DQS0 for DQ0-DQ7, DQS1 for DQ8-DQ15, and DQS2 for DQ16-
DQ23, DQS3 for DQ24-DQ31 in 16Mx32. Active on both edges for data input/output.
Center aligned to input data and edge aligned to output data.
UDM,
LDM
(DM0~3)
Input
Pulse
Active High In Write mode, DQM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high. If it’s high, LDM cor-
responds to DQ0-DQ7, and UDM corresponds to data on DQ8-DQ15 in 32Mx16. DM0
corresponds to DQ0-DQ7, DM1 corresponds to data on DQ8-DQ15, DM2 corresponds
to DQ16-DQ23, and DM3 corresponds to data on DQ24-DQ31 in 16Mx32.
Power and ground for the input buffers and the core logic.
VDD, VSS
VDDQ
VSSQ
NC
Supply
Supply
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Isolated power supply and ground for the output buffers to provide improved noise
immunity.
No connect.
Input
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Confidential
-5-
Rev.1.0
Sep.2014
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