STK12C68
64 Kbit (8 K x 8) AutoStore nvSRAM
Features
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Functional Description
The Cypress STK12C68 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB pin.
25 ns, 35 ns, and 45 ns access times
Hands off automatic STORE on power-down with external
68 µF capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Unlimited read, write, and recall cycles
1,000,000 STORE cycles to QuantumTrap
100 year data retention to QuantumTrap
Single 5 V + 10% operation
Commercial and industrial temperatures
228-pin (330 mil) SOIC, 28-pin (300 mil) PDIP, 28-pin (600 mil)
PDIP packages
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages
RoHS compliance
Logic Block Diagram
A
5
Quantum Trap
128 X 512
STORE
V
CC
V
CAP
A
7
A
8
A
9
A
11
A
12
ROW DECODER
A
6
POWER
CONTROL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
128 X 512
RECALL
HSB
SOFTWARE
DETECT
COLUMN I/O
A
0
-
A
12
DQ
0
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
INPUT BUFFERS
DQ
1
COLUMN DEC
A
0
A
1
A
2
A
3
A
4
A
10
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-51027 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 12, 2011
Not Recommended for New Designs. In production to support ongoing production programs only.
STK12C68
Contents
Not Recommended for New Designs. In production to support ongoing production programs only.
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
AutoStore Inhibit Mode .................................................... 5
Hardware STORE (HSB) Operation ................................. 5
Hardware RECALL (Power-up) ........................................ 5
Software STORE ............................................................... 5
Software RECALL ............................................................. 6
Data Protection ................................................................. 6
Noise Considerations ....................................................... 6
Hardware Protect .............................................................. 6
Low Average Active Power .............................................. 6
Preventing Store ............................................................... 6
Best Practices ................................................................... 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
DC Electrical Characteristics .......................................... 8
Data Retention and Endurance ....................................... 9
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Conditions .......................................................... 9
AC Switching Characteristics ....................................... 10
SRAM Read Cycle .................................................... 10
SRAM Write Cycle ..................................................... 11
AutoStore or Power-up RECALL ................................... 12
Software Controlled STORE/RECALL Cycle ................ 13
Hardware STORE Cycle ................................................. 14
Switching Waveform ...................................................... 14
Part Numbering Nomenclature ...................................... 15
Ordering Information ...................................................... 15
Package Diagrams .......................................................... 16
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Document Number: 001-51027 Rev. *F
Page 2 of 22
STK12C68
Pin Configurations
Figure 1. 28-Pin SOIC/DIP and LLC
Pin Definitions
Pin Name
A
0
–A
12
DQ
0
-DQ
7
WE
CE
OE
V
SS
V
CC
HSB
W
E
G
Alt
I/O Type
Input
Input
Input
Input
Ground
Description
Address Inputs.
Used to select one of the 8,192 bytes of the nvSRAM.
Write Enable Input, Active LOW.
When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
Ground for the Device.
The device is connected to ground of the system.
Input or Output
Bidirectional Data I/O Lines.
Used as input or output lines depending on operation.
Power Supply
Power Supply Inputs to the Device.
Input or Output
Hardware Store Busy (HSB).
When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
Power Supply
AutoStore Capacitor.
Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
V
CAP
Document Number: 001-51027 Rev. *F
Page 3 of 22
Not Recommended for New Designs. In production to support ongoing production programs only.
STK12C68
Device Operation
The STK12C68 nvSRAM is made up of two functional
components paired in the same physical cell. These are an
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK12C68 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL
operations from the nonvolatile cells and up to one million
STORE operations.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. A charge storage capacitor
between 68 µF and 220 µF (+20%) rated at 6 V should be
provided. The voltage on the V
CAP
pin is driven to 5 V by a
charge pump internal to the chip. A pull-up is placed on WE to
hold it inactive during power-up.
Figure 2. AutoStore Mode
SRAM Read
The STK12C68 performs a Read cycle whenever CE and OE are
LOW while WE and HSB are HIGH. The address specified on
pins A
0–12
determines the 8,192 data bytes accessed. When the
Read is initiated by an address transition, the outputs are valid
after a delay of t
AA
(Read cycle 1). If the Read is initiated by CE
or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever is later
(Read cycle 2). The data outputs repeatedly respond to address
changes within the t
AA
access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
10k Ohm
V
CAP
Vcc
WE
HSB
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the Write cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common I/O
pins DQ
0–7
are written into the memory if it has valid t
SD
, before
the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers t
HZWE
after WE goes
LOW.
Vss
AutoStore Operation
The STK12C68 stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power-down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the STK12C68.
In system power mode, both V
CC
and V
CAP
are connected to the
+5 V power supply without the 68
F
capacitor. In this mode, the
AutoStore function of the STK12C68 operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
CC
does not drop below 3.6 V during the 10 ms
STORE cycle.
To reduce unnecessary nonvolatile stores, AutoStore, and
Hardware Store operations are ignored, unless at least one Write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a Write operation has taken place. An
optional pull-up resistor is shown connected to HSB. The HSB
signal is monitored by the system to detect if an AutoStore cycle
is in progress.
Document Number: 001-51027 Rev. *F
Page 4 of 22
Not Recommended for New Designs. In production to support ongoing production programs only.
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
68 F
6v, +20%
0.1 F
Bypass
10k Ohm
STK12C68
Figure 3. AutoStore Inhibit Mode
0 .1 F
Bypass
10k Ohm
V
CAP
Vcc
WE
HSB
During any STORE operation, regardless of how it is initiated,
the STK12C68 continues to drive the HSB pin LOW, releasing it
only when the STORE is complete. After completing the STORE
operation, the STK12C68 remains disabled until the HSB pin
returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power-up)
During power-up or after any low power condition (V
CC
<
V
RESET
), an internal RECALL request is latched. When V
CC
once again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
If the STK12C68 is in a Write state at the end of power-up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 k resistor is connected either between WE and
system V
CC
or between CE and system V
CC
.
Vss
Software STORE
If the power supply drops faster than 20 us/volt before V
cc
reaches V
SWITCH
, then a 2.2
resistor should be connected
between V
CC
and the system supply to avoid momentary excess
of current between V
CC
and V
CAP
.
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK12C68 software STORE
cycle is initiated by executing sequential CE controlled Read
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of Reads from specific addresses is used
for STORE initiation, it is important that no other Read or Write
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following Read
sequence is performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
The software sequence is clocked with CE controlled Reads or
OE controlled Reads. When the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that Read cycles and not Write cycles
are used in the sequence. It is not necessary that OE is LOW for
a valid sequence. After the t
STORE
cycle time is fulfilled, the
SRAM is again activated for Read and Write operation.
AutoStore Inhibit Mode
If an automatic STORE on power loss is not required, then V
CC
is tied to ground and +5 V is applied to V
CAP
(Figure
3).
This is
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the STK12C68 is operated in this configuration,
references to V
CC
are changed to V
CAP
throughout this data
sheet. In this mode, STORE operations are triggered through
software control or the HSB pin. To enable or disable Autostore
using an I/O port pin see
Preventing Store
on page 6. It is not
permissible to change between these three options “on the fly”.
Hardware STORE (HSB) Operation
The STK12C68 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the STK12C68 conditionally initiates a STORE operation
after t
DELAY
. An actual STORE cycle only begins if a Write to the
SRAM takes place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress.
SRAM Read and Write operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
Document Number: 001-51027 Rev. *F
Page 5 of 22
Not Recommended for New Designs. In production to support ongoing production programs only.
1 0k O h m
the STK12C68 continues SRAM operations for t
DELAY
. During
t
DELAY
, multiple SRAM Read operations take place. If a Write is
in progress when HSB is pulled LOW, it allows a time, t
DELAY
to
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
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