STD7N60M2, STP7N60M2,
STU7N60M2
N-channel 600 V, 0.86
Ω
typ., 5 A MDmesh II Plus™ low Q
g
Power MOSFET in DPAK, TO-220 and IPAK packages
Datasheet
-
production data
Features
TAB
1
3
Order codes
STD7N60M2
STP7N60M2
STU7N60M2
V
DS
@
T
Jmax
650 V
R
DS(on)
max
0.95
Ω
I
D
DPAK
TAB
TAB
5A
•
Extremely low gate charge
1
3
2
1
2
3
•
Lower R
DS(on)
x area vs previous generation
•
Low gate input resistance
•
100% avalanche tested
•
Zener-protected
TO-220
IPAK
Figure 1. Internal schematic diagram
, TAB
Applications
•
Switching applications
Description
These devices are N-channel Power MOSFETs
developed using a new generation of MDmesh™
technology: MDmesh II Plus™ low Q
g
. These
revolutionary Power MOSFETs associate a
vertical structure to the company's strip layout to
yield one of the world's lowest on-resistance and
gate charge. They are therefore suitable for the
most demanding high efficiency converters.
AM15572v1
Table 1. Device summary
Order codes
STD7N60M2
STP7N60M2
STU7N60M2
7N60M2
Marking
Package
DPAK
TO-220
Tube
IPAK
Packaging
Tape and reel
June 2013
This is information on a product in full production.
DocID024622 Rev 1
1/21
www.st.com
Contents
STD7N60M2, STP7N60M2, STU7N60M2
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
6
Test circuits
.............................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
DocID024622 Rev 1
STD7N60M2, STP7N60M2, STU7N60M2
Electrical ratings
1
Electrical ratings
Table 2. Absolute maximum ratings
Symbol
V
GS
I
D
I
D
I
DM (1)
P
TOT
dv/dt
(1)
dv/dt
(2)
T
stg
T
j
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature
- 55 to 150
Max. operating junction temperature
°C
Parameter
Value
± 25
5
3.5
20
60
15
V/ns
50
Unit
V
A
A
A
W
1. I
SD
≤
5 A, di/dt
≤
400 A/µs; V
DS peak
< V
(BR)DSS
, V
DD
=400 V
2. V
DS
≤
480 V
Table 3. Thermal data
Value
Symbol
R
thj-case
R
thj-pcb
R
thj-amb
Parameter
DPAK TO-220 IPAK
Thermal resistance junction-case max
Thermal resistance junction-pcb max
(1)
Thermal resistance junction-ambient max
2.08
50
62.5
100
2.08
°C/W
°C/W
°C/W
Unit
1. When mounted on 1 inch² FR-4, 2 Oz copper board
Table 4. Avalanche characteristics
Symbol
I
AR
E
AS
Parameter
Avalanche current, repetitive or not repetitive (pulse width
limited by T
jmax
)
Single pulse avalanche energy (starting T
j
=25°C, I
D
= I
AR
;
V
DD
=50)
Value
1.5
99
Unit
A
mJ
DocID024622 Rev 1
3/21
21
Electrical characteristics
STD7N60M2, STP7N60M2, STU7N60M2
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 5. On /off states
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter
Drain-source
breakdown voltage
Test conditions
I
D
= 1 mA, V
GS
= 0
Min.
600
1
100
±10
2
3
0.86
4
0.95
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
V
DS
= 600 V
Zero gate voltage
drain current (V
GS
= 0) V
DS
= 600 V, T
C
=125 °C
Gate-body leakage
current (V
DS
= 0)
V
GS
= ± 25 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source
on-resistance
V
GS
= 10 V, I
D
= 2.5 A
Table 6. Dynamic
Symbol
C
iss
C
oss
C
rss
C
oss eq.(1)
R
G
Q
g
Q
gs
Q
gd
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Intrinsic gate
resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0
Test conditions
Min.
-
-
-
V
DS
= 0 to 480 V, V
GS
= 0
f = 1 MHz open drain
V
DD
= 480 V, I
D
= 5 A,
V
GS
= 10 V
(see
Figure 17)
-
-
-
-
-
Typ.
271
15.7
0.68
75.5
7.2
8.8
1.8
4.3
Max.
-
-
-
-
-
-
-
-
Unit
pF
pF
pF
pF
Ω
nC
nC
nC
1. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
Table 7. Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
DD
= 300 V, I
D
= 2.5 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
(see
Figure 16
and
21)
Test conditions
Min.
-
-
-
-
Typ.
7.6
7.2
19.3
15.9
Max.
-
-
-
-
Unit
ns
ns
ns
ns
4/21
DocID024622 Rev 1
STD7N60M2, STP7N60M2, STU7N60M2
Electrical characteristics
Table 8. Source drain diode
Symbol
I
SD
I
SDM
(1)
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
Min.
-
Typ.
Max. Unit
5
20
1.6
A
A
V
ns
nC
A
ns
nC
A
V
SD (2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
I
SD
= 5 A, V
GS
= 0
I
SD
= 5 A, di/dt = 100 A/µs
V
DD
= 60 V (see
Figure 18)
I
SD
= 5 A, di/dt = 100 A/µs
V
DD
= 60 V, T
j
= 150 °C
(see
Figure 18)
-
-
-
-
-
-
-
275
1.55
11
376
2.1
11
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID024622 Rev 1
5/21
21
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