12:2, Differential-to-3.3V, 2.5V
LVPECL Multiplexer
Datasheet
853S202
General Description
The 853S202 is a 12:2 Differential-to-LVPECL Clock Multiplexer
which can operate up to 3GHz. The 853S202 has twelve select-
able differential clock inputs, any of which can be independently
routed to either of the two LVDS outputs. The CLKx, nCLKx input
pairs can accept LVPECL or LVDS levels. The fully differential ar-
chitecture and low propagation delay make it ideal for use in clock
distribution circuits.
Features
• High speed 12.2 differential multiplexer
• Two differential 3.3V or 2.5V LVPECL outputs
• Twelve selectable differential clock or data inputs
• CLKx, nCLKx pairs can accept the following differential input
levels: LVPECL, LVDS
• Maximum output frequency: 3GHz
• Translates any single ended input signal to LVPECL levels with
resistor bias on nCLKx input
• Propagation delay: 1.15ns (maximum)
• Input skew: 150ps (maximum)
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS: 0.114ps (typical) @ 155.52MHz, 3.3V
• Full 3.3V or 2.5V operating supply mode
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
SELA_[3:0]
Pulldown
CLK0
Pulldown
nCLK0
Pullup/Pulldown
CLK1
Pulldown
nCLK1
Pullup/Pulldown
CLK2
Pulldown
nCLK2
Pullup/Pulldown
CLK3
Pulldown
nCLK3
Pullup/Pulldown
CLK4
Pulldown
nCLK4
Pullup/Pulldown
CLK5
Pulldown
Pullup/Pulldown
nCLK5
CLK6
Pulldown
nCLK6
Pullup/Pulldown
CLK7
Pulldown
nCLK7
Pullup/Pulldown
CLK8
Pulldown
nCLK8
Pullup/Pulldown
CLK9
Pulldown
Pullup/Pulldown
nCLK9
CLK10
Pulldown
nCLK10
Pullup/Pulldown
CLK11
Pulldown
nCLK11
Pullup/Pulldown
SELB_[3:0]
Pulldown
4
Pullup
4
Pin Assignment
nCLK1
CLK1
V
EE
nCLK0
CLK0
V
CC
OEB
CLK11
nCLK11
V
EE
CLK10
nCLK10
CLK2
nCLK2
SELA_0
SELA_1
V
CC
QA
nQA
V
EE
SELA_2
SELA_3
CLK3
nCLK3
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
2
34
3
33
4
48-Pin LQFP
32
5
6
7mm x 7mm x 1.4mm
31
30
7
package body
29
8
Y Package
28
9
Top View
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
853S202
ICS853S202I
QA
nQA
Pullup
OEA
CLK9
nCLK9
SELB_0
SELB_1
V
CC
QB
nQB
V
EE
SELB_2
SELB_3
CLK8
nCLK8
QB
nQB
OEB
©2016 Integrated Device Technology, Inc.
1
nCLK4
CLK4
V
EE
nCLK5
CLK5
V
CC
OEA
CLK6
nCLK6
V
EE
CLK7
nCLK7
Revision B, October 4, 2016
853S202 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3,
4,
9,
10
5, 18, 32, 43
6, 7
8, 15, 22, 29,
39, 46
11
12
13
14
16
17
19
20
21
23
24
25
26
27,
28,
33,
34
30, 31
35
36
37
38
Name
CLK2
nCLK2
SELA_0,
SELA_1,
SELA_2,
SELA_3
V
CC
QA, nQA
V
EE
CLK3
nCLK3
nCLK4
CLK4
nCLK5
CLK5
OEA
CLK6
nCLK6
CLK7
nCLK7
nCLK8
CLK8
SELB_3,
SELB_2,
SELB_1,
SELB_0
nQB, QB
nCLK9
CLK9
nCLK10
CLK10
Input
Input
Type
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Input
Pulldown
Clock select pins for Bank A output pair. See Control Input Function Table.
LVCMOS/LVTTL interface levels. See Table 3B.
Power supply pins.
Clock outputs. LVDS interface levels.
Power supply ground.
Power
Output
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Output enable pin. Controls enabling and disabling of QA, nQA output pair.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Clock select pins for Bank B output pair. See Control Input Function Table.
LVCMOS/LVTTL interface levels. See Table 3C.
Clock outputs. LVDS interface levels.
Input
Pulldown
Output
Input
Input
Input
Input
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
©2016 Integrated Device Technology, Inc.
2
Revision B, October 4, 2016
853S202 Datasheet
Table 1. Pin Descriptions
Number
40
41
42
44
45
47
48
Name
nCLK11
CLK11
OEB
CLK0
nCLK0
CLK1
nCLK1
Input
Input
Input
Input
Input
Input
Input
Type
Pullup/
Pulldown
Pulldown
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Output enable pin. Controls enabling and disabling of QB, nQB output pair.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3A. OEA, OEB Control Input Function Table
Input
OEA, OEB
0
1
Output
QA, nQA, QB, nQB
Disabled (Logic LOW)
Active (default)
©2016 Integrated Device Technology, Inc.
3
Revision B, October 4, 2016
853S202 Datasheet
Table 3B. SEL_A Control Input Function Table
Control Input
Input Selected to QA, nQA
SELA_3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SELA_2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SELA_1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SELA_0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK0, nCLK0 (default)
CLK1, nCLK1
CLK2, nCLK2
CLK3, nCLK3
CLK4, nCLK4
CLK5, nCLK5
CLK6, nCLK6
CLK7, nCLK7
CLK8, nCLK8
CLK9, nCLK9
CLK10, nCLK10
CLK11, nCLK11
Output at logic LOW
Output at logic LOW
Output at logic LOW
Output at logic LOW
Table 3C. SEL_B Control Input Function Table
Control Input
Input Selected to QA, nQA
SELB_3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SELB_2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SELB_1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SELB_0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK0, nCLK0 (default)
CLK1, nCLK1
CLK2, nCLK2
CLK3, nCLK3
CLK4, nCLK4
CLK5, nCLK5
CLK6, nCLK6
CLK7, nCLK7
CLK8, nCLK8
CLK9, nCLK9
CLK10, nCLK10
CLK11, nCLK11
Output at logic LOW
Output at logic LOW
Output at logic LOW
Output at logic LOW
©2016 Integrated Device Technology, Inc.
4
Revision B, October 4, 2016
853S202 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
70.2C/W (0 lfpm)
-65C to 150C
DC Characteristic Tables
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Core Supply Voltage
Power Supply Current
No Load
Test Conditions
Minimum
3.135
Typical
3.3
85
Maximum
3.465
95
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Core Supply Voltage
Power Supply Current
No Load
Test Conditions
Minimum
2.375
Typical
2.5
80
Maximum
2.625
88
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
Input Low Voltage
SELA_[3:0],
SELB_[3:0]
OEA,
OEB
SELA_[3:0],
SELB_[3:0]
OEA,
OEB
V
CC
= 3.3V
V
CC
= 2.5V
Input High
Current
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
-5
-150
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
A
A
A
A
V
IL
I
IH
I
IL
Input Low
Current
©2016 Integrated Device Technology, Inc.
5
Revision B, October 4, 2016
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