Si51214 Data Sheet
Two Output Factory Programmable Clock Generator
The factory programmable Si51214 is the industry’s lowest power, smallest footprint and
frequency flexible programmable clock generator targeting low power, low cost and high
volume consumer and embedded applications. The device operates from a single crys-
tal or an external clock source and generates 1 to 2 outputs up to 133 MHz. The device
is factory programmed to provide customized output frequencies and control input such
as frequency select, spread spectrum on, power down and output enable. Center spread
spectrum can also be programmed to reduce EMI to meet board level system require-
ments.
Applications
• Crystal/XO replacement
• EMI reduction
• Portable devices
• Digital still camera
• IP phone
• Smart meter
KEY FEATURES
• Generates up to 2 CMOS clock outputs
from 3 to 133 MHz
• Accepts crystal or reference clock input
• 3 to 165 MHz reference clock input
• 8 to 48 MHz crystal input
• Programmable FSEL, SSONb, PD, and OE
input functions
XIN/
2
CLKIN
PLL with
Modulation
Control
XOUT 3
Programmable
Configuration
Register
Buffers,
Dividers,
and
Switch
Matrix
4 SSCLK1/
REFCLK/
OE/FSEL/SSONb
VDD 1
VSS 6
V-REG
To Core
To Pin 4 and Pin
5
5 SSCLK2/OE/
SSONb/PD
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Si51214 Data Sheet
Feature List
1. Feature List
The Si51214 highlighted features are listed below.
• Generates up to 2 CMOS clock outputs from 3 to 133 MHz
• Accepts crystal or reference clock input
• 3 to 165 MHz reference clock input
• 8 to 48 MHz crystal input
• Programmable FSEL, SSONb, PD, and OE input functions
• Low power dissipation
•
•
•
•
1.8 V voltage supply range
±0.25%, ±0.5% or ±1% spread spectrum (center spread)
Low cycle-cycle jitter
Ultra small 6-pin TDFN package (1.2 mm x 1.4 mm)
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Si51214 Data Sheet
Design Considerations
2. Design Considerations
2.1 Typical Application Schematic
2.2 Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1 μF must be used between VDD and VSS on pin 1. Place the capacitor on the
component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as
short as possible. Do not use vias between the decoupling capacitor and the VDD pin. In addition, a 10 µF capacitor should be placed
between VDD and VSS.
Series Termination Resistor:
A series termination resistor is recommended if the distance between the outputs (SSCLK or REFCLK
pins) and the load is over 1 ½ inches. The nominal impedance of the SSCLK output is about 30 Ω. Use a 20 Ω resistor in series with the
output to terminate a 50 Ω trace impedance and place a 20 Ω resistor as close to the SSCLK output as possible.
Crystal and Crystal Load:
Only use a parallel resonant fundamental AT cut crystal. Do not use higher overtone crystals. To meet the
crystal initial accuracy specification (in ppm) make sure that the external crystal load capacitor is matched to the crystal load specifica-
tion. To determine the value of CL1 and CL2, use the following formula:
CL1 = CL2 = 2CL − (Cpin + Cp);
where CL is the load capacitance stated by the crystal manufacturer,
Cpin is the Si51214 pin capacitance (3 pF), and
Cp is the parasitic capacitance of the PCB traces.
Example:
If a crystal with CL = 12 pF specification is used and Cp = 1 pF (parasitic PCB capacitance on PCB), 19 or 20 pF external
capacitors from pins XIN (pin 2) and XOUT (Pin 3) to VSS are required. Users must verify Cp value.
Table 2.1. Crystal Specifications
Equivalent Series Resistance (ESR)
< 50 Ω
Crystal Output Capacitance (CO)
< 3 pF
Load Capacitance (CL)
< 13 pF
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Si51214 Data Sheet
Electrical Specifications
3. Electrical Specifications
Table 3.1. DC Electrical Specifications
(V
DD
= 1.8 V ±5%, C
L
= 10 pF, T
A
= –40 to 85 °C)
Parameter
Operating Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Operating Supply Current
1
Symbol
V
DD
V
OH
V
OL
V
IH
V
IL
I
DD
Test Condition
V
DD
= 1.8 V ± 5%
I
OH
= –4 mA
I
OL
= 4 mA
CMOS Level
CMOS Level
F
IN
= 12 MHz, SSCLK1 = 12 MHz,
SSCLK2 = 24 MHz, C
L
= 5 pF, V
DD
= 1.8 V
Min
1.71
V
DD
– 0.5
—
0.7 V
DD
0
—
Typ
1.8
—
—
—
—
5.5
Max
1.89
—
0.3
—
0.3 V
DD
9
Unit
V
V
V
V
V
mA
Power Down Current
Nominal Output Impedance
Internal Pull-up/Pull-down Resistor
Input Pin Capacitance
Load Capacitance
Note:
IDD
PD
Z
O
R
PUP
/R
PD
C
IN
C
L
Pin 5
Input pin capacitance
Clock outputs
—
—
—
—
—
0.5
30
150k
3
—
0.65
—
—
5
10
mA
Ω
Ω
pF
pF
1. I
DD
depends on input and output frequency configurations.
Table 3.2. AC Electrical Specifications
(V
DD
= 1.8 V ±5%, C
L
= 10 pF, T
A
= –40 to 85 °C)
Parameter
Input Frequency Range
Input Frequency Range
Output Frequency Range
Frequency Accuracy
Output Duty Cycle
Symbol
F
IN1
F
IN2
F
OUT
F
ACC
DC
OUT
Condition
Crystal input
Reference clock Input
SSCLK1/2
Configuration dependent
Measured at V
DDO
/2
F
OUT
< 75 MHz
Measured at V
DDO
/2
F
OUT
> 75 MHz
Input Duty Cycle
Output Rise/Fall Time
DC
IN
t
r
/t
f
CLKIN, CLKOUT through PLL
C
L
= 10 pF, 20 to 80%
30
—
50
1
70
2
%
ns
40
50
60
%
Min
8
3
3
—
45
Typ
—
—
—
0
50
Max
48
165
133
—
55
Unit
MHz
MHz
MHz
ppm
%
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Si51214 Data Sheet
Electrical Specifications
Parameter
Period Jitter
Symbol
PJ
1
PJ
2
Cycle-to-Cycle Jitter
CCJ
1
CCJ
2
Power-up Time
Output Enable Time
t
PU
t
OE
Condition
SSCLK1/2, at the same frequency
SSCLK1/2, at different output fre-
quencies
1
SSCLK1/2, at the same frequency
SSCLK1/2, at different output fre-
quencies
1
Time from 0.9 V
DD
to valid
frequencies at all clock outputs
Time from OE rising edge to active
at outputs SSCLK1/2 (asynchro-
nous), F
OUT
= 133 MHz
Time from OE falling edge to active
at outputs SSCLK1/2 (asynchro-
nous), F
OUT
= 133 MHz
Min
—
—
—
—
—
—
Typ
15
35
100
150
1.2
15
Max
30
105
2
200
305
2
5
—
Unit
ps rms
ps rms
ps
ps
ms
ns
Output Disable Time
t
OD
—
15
—
ns
Spread Spectrum Modulation Rate
3
SS
DEV
—
37
—
kHz
Note:
1. Example frequency configurations:
• 100 MHz, 75 MHz
• 100 MHz, 66 2/3 MHz
• 96 MHz, 133 1/3 MHz
2. Jitter performance depends on configuration and programming parameters.
3. The SS modulation rate is a fixed ratio of the reference frequency with values in the range of 30 kHz to 50 kHz based on the
frequency plan.
Table 3.3. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
ESD Protection (Human Body Mod-
el)
ESD Protection (Charge Device
Model)
ESD Protection (Machine Model)
Symbol
V
DD
V
IN
T
S
T
A
ESD
HBM
ESD
CDM
ESD
MM
Relative to V
SS
Non-functional
Functional, I-temp
JEDEC (JESD 22-A114)
JEDEC (JESD 22-C101)
JEDEC (JESD 22-A115)
Condition
Min
–0.5
–0.5
–65
–40
–4000
–1500
–200
Typ
—
—
—
—
—
—
—
Max
2.4
V
DD
+0.5
150
85
4000
1500
200
Unit
V
V
°C
°C
V
V
V
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