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74VCX162373 Low Voltage 16-Bit Transparent Latch
January 2000
Revised June 2005
74VCX162373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
and 26: Series Resistors in Outputs
General Description
The VCX162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The VCX162373 is also designed with 26
:
resistors in the
outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers and bus
transceivers/transmitters.
The 74VCX162373 is designed for low voltage (1.4V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.4V–3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
26
:
series resistors in outputs
s
t
PD
(I
n
to O
n
)
3.3 ns max for 3.0V to 3.6V V
CC
s
Power-off high impedance inputs and outputs
s
Support live insertion and withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
r
12 mA @ 3.0V V
CC
s
Uses proprietary noise/EMI reduction circuitry
s
Latch-up performance exceeds 300 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
百度来的资料。。。。。大家分享
Martin,
You can use CCS v5.1 today with Matlab via the xmakeilesetup infrastructure provided for CCSv4.
To do so, follow these instruction ......
EtherCAT（Ethernet for Control Automation Technology）是一种基于以太网的开发构架的实时工业现场总线通讯协议，EtherCAT是最快的工业以太网技术之一，同时它提供纳秒级精确同步。相对于设置了相同循环时间的其他总线系统，EtherCAT系统结构通常能减少25%-30%的CPU负载，EtherCAT的出现为系统的实时性能和拓扑的灵活性树立了新的标准。...[详细]
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