CYFB0072V
72-Mbit Video Frame Buffer
72-Mbit Video Frame Buffer
Features
■
Functional Description
The Video Frame Buffer is a 72-Mbit memory device which
operates as a FIFO with a bus width of 36 bits. It has independent
read and write ports, which can be clocked up to 133 MHz. The
bus size of 36 bits enables a data throughput of 4.8 Gbps. The
device also offers a simple and easy-to-use interface to reduce
implementation and debugging efforts, improve time-to-market,
and reduce engineering costs. This makes it an ideal memory
choice for a wide range of applications including video and image
processing or any system that needs buffering at high speeds
across different clock domains.
The functionality of the Video Frame Buffer is such that the data
is read out of the read port in the same sequence in which it was
written into the write port. If writes and inputs are enabled (WEN
& IE), data on the write port gets written into the device at the
rising edge of write clock. Enabling reads and outputs (REN &
OE) fetches data on the read port at every rising edge of read
clock. Both reads and writes can occur simultaneously at
different speeds provided the ratio between read and write clock
is in the range of 0.5 to 2. Appropriate flags are set whenever the
device is empty or full.
The device also supports a flow-through mailbox register to
bypass the frame buffer memory
For a complete list of related documentation,
click here.
Memory organization
❐
Density: 72-Mbit
❐
Organization: × 36
Up to 133-MHz clock operation
[1]
Unidirectional operation
Independent read and write ports
❐
Supports simultaneous read and write operations
❐
Reads and writes operate on independent clocks, upto a
maximum ratio of two, enabling data buffering across clock
domains.
❐
Supports multiple I/O voltage standard: low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
Input and output enable control for write mask and read skip
operations
Empty & Full status flags
Flow-through mailbox register to send data from input to output
port, bypassing the Frame Buffer
Separate serial clock (SCLK) input for serial programming of
configuration registers
Master reset to clear entire Frame Buffer
Partial reset to clear data but retain programmable settings
Joint test action group (JTAG) port provided for boundary scan
function
Industrial temperature range: –40 °C to +85 °C
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Note
1. For device operating at 150 MHz, Contact Sales.
Cypress Semiconductor Corporation
Document Number: 001-88646 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 14, 2017
CYFB0072V
Logic Block Diagram
D[35:0]
IE
WEN
WCLK
LD
SPI_SEN SPI_SCLK
INPUT
REGISTER
WRITE
CONTROL LOGIC
CONFIGURATION
REGISTERS/MAILBOX
SPI_SI
MB
FF
WRITE POINTER
Memory Array
MRS
PRS
FLAG LOGIC
EF
DVal
RESET POINTER
72-Mbit
READ POINTER
TCK
TMS
TDO
TDI
JTAG CONTROL
READ CONTROL
LOGIC
OUTPUT
REGISTER
RCLK
REN
OE
Q[35:0]
Document Number: 001-88646 Rev. *E
Page 2 of 28
CYFB0072V
Contents
Pin Configuration ............................................................. 4
Pin Definitions .................................................................. 5
Architecture ...................................................................... 7
Reset Logic ................................................................. 7
Data Valid Signal (DVal) .............................................. 7
Write Mask and Read Skip Operation ......................... 7
Flow-through Mailbox Register .................................... 7
Flag Operation............................................................. 7
Programming Configuration Registers ........................ 8
Width Expansion Configuration ................................. 11
Power Up ................................................................... 11
Read/Write Clock Requirements ............................... 11
JTAG Operation ........................................................ 12
Test Access Port ....................................................... 12
Tap Registers ............................................................ 12
JTAG ID Codes ......................................................... 13
OPCODES Supported ............................................... 13
JTAG Instructions ...................................................... 13
Instruction Update and Bypass ................................. 13
TAP Controller State Diagram ................................... 13
Maximum Ratings ........................................................... 14
Operating Range ............................................................. 14
Recommended DC Operating Conditions .................... 14
Electrical Characteristics ............................................... 14
I/O Characteristics .......................................................... 15
Latency Table .................................................................. 15
AC Test Load Conditions ............................................... 16
Switching Characteristics .............................................. 17
Switching Waveforms .................................................... 18
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC® Solutions ...................................................... 28
Cypress Developer Community ................................. 28
Technical Support ..................................................... 28
Document Number: 001-88646 Rev. *E
Page 3 of 28
CYFB0072V
Pin Configuration
Figure 1. 209-ball FBGA pinout (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
FF
EF
D4
D6
D8
D10
D12
D14
D16
DNU
D18
D20
D22
D24
D26
D28
DVal
DNU
TDO
2
D0
D2
D5
D7
D9
D11
D13
D15
D17
DNU
D19
D21
D23
D25
D27
D29
DNU
DNU
DNU
3
D1
D3
WEN
V
SS
V
CC2
V
SS
V
CC2
V
SS
V
CC2
WCLK
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
SS
D30
D32
D34
4
DNU
DNU
DNU
V
CC1
V
CC2
V
SS
V
CC2
V
SS
V
CC2
DNU
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
CC1
D31
D33
D35
5
V
PU
DNU
V
CC1
DNU
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
CC1
PRS
DNU
TDI
6
V
PU
V
PU
DNU
LD
V
CCIO
DNU
V
CC1
V
CC1
V
CC1
IE
V
CC1
V
CC1
V
CC1
SPI_SEN
V
CCIO
SPI_SI
DNU
[2]
MRS
DNU
7
DNU
DNU
V
CC1
DNU
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
CC1
SPI_SCLK
MB
TMS
8
DNU
DNU
DNU
V
CC1
V
CC2
V
SS
V
CC2
V
SS
V
CC2
DNU
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
CC1
V
REF
DNU
TCK
9
V
PD
REN
RCLK
Vss
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
CCIO
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
SS
OE
V
PD
DNU
10
Q0
Q2
Q4
Q6
Q8
Q10
Q12
Q14
Q16
V
CCIO
Q18
Q20
Q22
Q24
Q26
Q28
Q30
Q32
Q34
11
Q1
Q3
Q5
Q7
Q9
Q11
Q13
Q15
Q17
V
CCIO
Q19
Q21
Q23
Q25
Q27
Q29
Q31
Q33
Q35
Notes
2. This pin should be tied to V
SS
preferably or can be left floating to ensure normal operation.
Document Number: 001-88646 Rev. *E
Page 4 of 28
CYFB0072V
Pin Definitions
Pin Name
MRS
PRS
WCLK
LD
WEN
IE
I/O
Input
Input
Input
Input
Input
Input
Pin Description
Master reset: MRS initializes the internal read and write pointers to zero, resets both flags and sets the
output register to all zeroes. During Master Reset, the configuration registers are set to default values.
Partial reset: PRS initializes the internal read and write pointers to zero, resets both flags and sets the
output register to all zeroes. During Partial Reset, the configuration register settings are retained.
Write clock: The rising edge clocks data into the frame buffer when writes are enabled (WEN asserted).
Data is written into the buffer memory when LD is high and into configuration registers when LD is low.
Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the buffer memory.
Write enable: Control signal to enable writes to the device. When WEN is low data present on the inputs
is written to the buffer memory or configuration registers on every rising edge of WCLK.
Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on input pins is written into the frame buffer memory or configuration
registers. The internal write address pointer is always incremented at rising edge of WCLK if WEN is
enabled, regardless of the IE level. This is used for 'write masking' or incrementing the write pointer
without writing into a location.
Data inputs: Data inputs for a 36-bit bus.
Read clock: The rising edge initiates a read from the frame buffer when reads are enabled (REN
asserted). Data is read from the buffer memory when LD is high & from the configuration registers if LD
is low.
Read enable: Control signal to enable reads from the device. When REN is low data is read from the
buffer memory or configuration registers on every rising edge of RCLK.
Output enable: When OE is LOW, device data outputs are enabled; when OE is HIGH, the device’s
outputs are in High Z (high impedance) state.
Data outputs: Data outputs for a 36-bit bus.
Data valid: Active low data valid signal to indicate valid data on Q[35:0].
Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
Empty flag: When EF is LOW, the frame buffer is empty. EF is synchronized to RCLK.
Full flag: When FF is LOW, the frame buffer is full. FF is synchronized to WCLK.
Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the
configuration registers if SPI_SEN is enabled.
Serial input: Serial input data in SPI mode.
Serial enable: Enables serial loading of configuration registers.
Test clock (TCK) pin for JTAG.
Test mode select (TMS) pin for JTAG.
Test data in (TDI) pin for JTAG.
Test data out (TDO) pin for JTAG.
D[35:0]
RCLK
Input
Input
REN
OE
Q[35:0]
DVal
MB
EF
FF
SPI_SCLK
SPI_SI
SPI_SEN
TCK
TMS
TDI
TDO
V
REF
V
CC1
V
CC2
Input
Input
Output
Output
Input
Output
Output
Input
Input
Input
Input
Input
Input
Output
Input
Reference voltage: Reference voltage (regardless of I/O standard used)
Reference
Power
Supply
Power
Supply
Core voltage supply 1: 1.8 V supply voltage
Core voltage supply 2: 1.5 V supply voltage
Document Number: 001-88646 Rev. *E
Page 5 of 28
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