NL17SZ32
Single 2-Input OR Gate
The NL17SZ32 is a single 2−input OR Gate in three tiny footprint
packages. The device performs much as LCX multi−gate products in
speed and drive. They should be used wherever the need for higher
speed and drive are needed.
Features
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MARKING
DIAGRAMS
1
SC−88A
(SC−70−5/SOT−353)
DF SUFFIX
CASE 419A
5
1
SOT−553
XV5 SUFFIX
CASE 463B
5
L4 M
G
G
1
•
•
•
•
•
•
•
•
Tiny SOT−353, SOT−553 and SOT−953 Packages
2.4 ns T
PD
at 5.0 V (typ)
Source/Sink 24 mA at 3.0 V
Over−Voltage Tolerant Inputs
Pin For Pin with NC7SZ32P5X, TC7SZ32FU and TC7SZ32AFE
Chip Complexity: FETs = 20
Designed for 1.65 V to 5.5 V V
CC
Operation
These Devices are Pb−Free, Halogen Free, Beryllium Free and are
RoHS Compliant
B
1
A
2
V
CC
5
IN A
1
GND
2
Y
4
IN B
3
OUT Y
4
V
CC
5
5
5
L4 M
G
G
1
GND
3
L4 = Specific Device Marking
M = Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
SOT−953
SOT−353/SC70−5/
SC−88A
IN B
1
V
CC
6
3
M
SOT−953
CASE 527AE
1
= Specific Device Code
= Month Code
UDFN6
1.0 x 1.0
CASE 517BX
(In Development)
T = Specific Device Code
M = Date Code
3M
IN A
2
NC
5
1
1
Figure 1. Pinouts
(Top View)
A
B
w1
A
M
Y
= Specific Device Code
= Date Code
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
November, 2015 − Rev. 17
Publication Order Number:
NL17SZ32/D
A
GND
3
OUT Y
4
UDFN6
1.45 x 1.0
CASE 517AQ
(In Development)
T
M
M
NL17SZ32
PIN ASSIGNMENT
(SOT−353/SC70−5/SC−88A/SOT−553)
Pin
1
2
3
4
5
Function
B
A
GND
Y
V
CC
PIN ASSIGNMENT
(SOT−953)
Pin
1
2
3
4
5
Function
IN A
GND
IN B
OUT Y
V
CC
FUNCTION TABLE
Output
Input
A
L
L
H
H
B
L
H
L
H
Y=A+B
Y
L
H
H
H
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
V
OUT
I
IK
I
OK
I
OK
I
OUT
I
CC
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
ESD
I
LATCHUP
DC Supply Voltage
DC Input Voltage
DC Output Voltage (SOT−353/SC70−5/SC−88A/SOT−553 Packages)
DC Output Voltage
(SOT−953 Package)
DC Input Diode Current
DC Output Diode Current
(SOT−353/SC70−5/SC−88A/SOT−553 Packages)
DC Output Diode Current (SOT−953 Package)
DC Output Sink Current
DC Supply Current per Supply Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
Power Dissipation in Still Air at 85°C
Moisture Sensitivity
Flammability Rating
ESD Classification
Oxygen Index: 28 to 34
Human Body Model (Note 2)
Machine Model (Note 3)
SOT−353 (Note 1)
SOT−553
SOT−353
SOT−553
V
OUT
< GND, V
OUT
> V
CC
V
OUT
< GND
Output at High or Low State
Power−Down Mode (V
CC
= 0 V)
Parameter
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to V
CC
+0.5
−0.5 to V
CC
+ 0.5
−0.5 to + 0.5
−50
±50
−50
±50
±100
*65
to +150
260
+150
350
496
186
135
Level 1
UL 94 V−0 @ 0.125 in
2000
200
±100
V
mA
Units
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
mW
Latchup Performance Above V
CC
and Below GND at 125°C (Note 4)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A, rated to EIA/JESD22−A114−B.
3. Tested to EIA/JESD22−A115−A, rated to EIA/JESD22−A115−A.
4. Tested to EIA/JESD78.
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2
NL17SZ32
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
V
OUT
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage (SOT−353/SC70−5/SC−88A/SOT−553 Packages)
DC Output Voltage (SOT−953 Package)
Operating Temperature Range
Input Rise and Fall Time
V
CC
= 3.0 V
±0.3
V
V
CC
= 5.0 V
±0.5
V
Parameter
Min
1.65
0
0
0
−55
0
0
Max
5.5
5.5
5.5
V
CC
+125
100
20
Units
V
V
V
V
°C
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
V
CC
Symbol
V
IH
V
IL
V
OH
Parameter
High−Level Input Voltage
Low−Level Input Voltage
High−Level Output Voltage
V
IN
= V
IL
or V
IH
I
OH
= −100
mA
I
OH
= −3 mA
I
OH
= −8 mA
I
OH
= −12 mA
I
OH
= −16 mA
I
OH
= −24 mA
I
OH
= −32 mA
V
OL
Low−Level Output Voltage
V
IN
= V
IH
or V
OH
I
OL
= 100
mA
I
OL
= 3 mA
I
OL
= 8 mA
I
OL
= 12 mA
I
OL
= 16 mA
I
OL
= 24 mA
I
OL
= 32 mA
I
IN
I
OFF
Input Leakage Current
Power
Off
Leakage
Current
(SOT−353/
SC70−5/SC−88A/
SOT−553 Packages)
Quiescent Supply Current
V
IN
= 5.5 V or GND
V
IN
= 5.5 V or
V
OUT
= 5.5 V
Condition
(V)
1.65 to 1.95
2.3 to 5.5
1.65 to 1.95
2.3 to 5.5
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
0 to 5.5
0
0.08
0.20
0.22
0.28
0.38
0.42
V
CC
− 0.1
1.29
1.9
2.2
2.4
2.3
3.8
V
CC
1.52
2.1
2.4
2.7
2.5
4.0
0.1
0.24
0.3
0.4
0.4
0.55
0.55
±0.1
1
Min
0.75 V
CC
0.7 V
CC
0.25 V
CC
0.3 V
CC
V
CC
− 0.1
1.29
1.9
2.2
2.4
2.3
3.8
0.1
0.24
0.3
0.4
0.4
0.55
0.55
±1.0
10
mA
mA
V
T
A
= 255C
Typ
Max
−555C
3
T
A
3
1255C
Min
0.75 V
CC
0.7 V
CC
0.25 V
CC
0.3 V
CC
Max
Units
V
V
V
I
CC
V
IN
= 5.5 V or GND
5.5
1
10
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
NL17SZ32
AC ELECTRICAL CHARACTERISTICS
t
R
= t
F
= 3.0 ns
V
CC
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
(Figure 3 and 4)
Condition
R
L
= 1 MW, C
L
= 15 pF
R
L
= 1 MW, C
L
= 15 pF
R
L
= 1 MW, C
L
= 15 pF
R
L
= 1 MW, C
L
= 15 pF
R
L
= 500
W,
C
L
= 50 pF
R
L
= 1 MW, C
L
= 15 pF
R
L
= 500
W,
C
L
= 50 pF
5.0
±
0.5
(V)
1.65
1.8
2.5
±
0.2
3.3
±
0.3
Min
2.0
2.0
0.8
0.5
1.5
0.5
0.8
T
A
= 255C
Typ
5.5
4.6
3.0
2.6
3.0
2.2
2.4
Max
12.0
10
7
4.7
5.2
4.1
4.5
−555C
3
T
A
3
1255C
Min
2.0
2.0
0.8
0.5
1.5
0.5
0.8
Max
12.7
10.5
7.5
5.0
5.5
4.4
4.8
Units
ns
CAPACITIVE CHARACTERISTICS
Symbol
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(Note 5)
Parameter
Condition
V
CC
= 5.5 V, V
I
= 0 V or V
CC
10 MHz, V
CC
= 3.3 V, V
I
= 0 V or V
CC
10 MHz, V
CC
= 5.5 V, V
I
= 0 V or V
CC
Typical
u4
25
30
Units
pF
pF
5. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the no−load dynamic
power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
t
f
= 3 ns
90%
90%
50%
10%
t
f
= 3 ns
V
CC
INPUT
GND
R
L
t
PHL
t
PLH
V
OH
C
L
OUTPUT
INPUT
A and B
50%
10%
OUTPUT Y
50%
50%
V
OL
A 1 MHz square input wave is recommended for
propagation delay tests.
Figure 3. Switching Waveform
ORDERING INFORMATION
Device Order Number
NL17SZ32DFT2G
NL17SZ32XV5T2G
NL17SZ32P5T5G
NL17SZ32MU1TCG
(In Development)
NL17SZ32MU3TCG
(In Development)
Package Type
SC−88A/SC−70−5/SOT−353
(Pb−Free)
SOT−553
(Pb−Free)
SOT−953
(Pb−Free)
UDFN6, 1.45 x 1.0, 0.5P
(Pb−Free)
UDFN6, 1.0 x 1.0, 0.35P
(Pb−Free)
Figure 4. Test Circuit
Tape and Reel Size
†
3000 / Tape & Reel
4000 / Tape & Reel
8000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NL17SZ32
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
A
G
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
S
1
2
3
−B−
DIM
A
B
C
D
G
H
J
K
N
S
D
5 PL
0.2 (0.008)
M
B
M
N
J
C
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
---
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
---
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
H
K
SOLDER FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
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