HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
IDT70V05S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V05S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V05L
Active: 380mW (typ.)
Standby: 660
µ
W (typ.)
IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
◆
◆
◆
◆
◆
◆
◆
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◆
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1,2)
,
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
A
12R
A
0R
(1,2)
A
12L
A
0L
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R
(2)
2942 drw 01
MARCH 2018
1
©2018 Integrated Device Technology, Inc.
DSC 2941/11
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port
SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bit-
or-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM
approach in 16-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 400mW of power.
The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
Pin Configurations
(1,2,3)
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
V
SS
I/O
6L
I/O
7L
V
DD
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
1L
I/O
0L
N/C
OE
L
R/W
L
SEM
L
CE
L
N/C
N/C
V
DD
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
9
8 7
6
5 4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
12/03/01
IDT70V05J
J68-1
(4)
68-Pin PLCC
Top View
(5)
55
54
53
52
51
50
49
48
47
46
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
2941 drw 02
,
I/O
7R
N/C
OE
R
R/W
R
SEM
R
CE
R
N/C
N/C
V
SS
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
I/O
1L
I/O
0L
OE
L
R/W
L
SEM
L
12/03/01
INDEX
54
53
52
64
63
62
59
58
57
56
55
61
60
51
50
49
CE
L
N/C
V
DD
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
5L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
V
SS
I/O
6L
I/O
7L
V
DD
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
,
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
2941 drw 03
70V05PF
PN-64
(4)
64-Pin TQFP
Top View
(5)
R/W
R
SEM
R
CE
R
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
26
27
28
23
24
25
29
30
31
A
8R
A
7R
17
18
19
I/O
6R
I/O
7R
OE
R
N/C
GND
A
12R
A
11R
A
10R
A
9R
6.42
2
A
6R
A
5R
32
16
20
21
22
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
12/03/01
51
A
5L
11
53
A
7L
55
A
9L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
40
38
A
0L
BUSY
L
M/S
INT
R
A
1R
45
43
INT
L
V
SS
41
39
37
BUSY
R
A
0R
A
2R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
34
A
5R
33
A
6R
31
A
8R
52
A
6L
54
A
8L
10
09
08
56
57
A
11L
A
10L
59
V
DD
58
A
12L
07
06
60
61
N/C
N/C
62
63
SEM
L
CE
L
64
65
OE
L
R/W
L
67
66
I/O
0L
N/C
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
4
I/O
3L
I/O
5L
B
C
5
V
SS
IDT70V05G
G68-1
(4)
68-Pin PGA
Top View
(5)
29
28
A
11R
A
10R
26
V
SS
24
N/C
27
A
12R
25
N/C
05
04
23
22
SEM
R
CE
R
21
20
OE
R
R/W
R
7
9
I/O
7L
V
SS
11
13
15
I/O
1R
V
DD
I/O
4R
18
19
I/O
7R
N/C
17
I/O
6R
K
L
2941 drw 04
03
02
01
A
INDEX
6
8
10
12
14
16
I/O
6L
V
DD
I/O
0R
I/O
2R
I/O
3R
I/O
5R
D
E
F
G
H
J
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking.
Pin Names
Left Port
CE
L
R/
W
L
OE
L
A
0
L
- A
12
L
I/O
0
L
- I/O
7
L
SEM
L
INT
L
BUSY
L
CE
R
R/
W
R
OE
R
A
0
R
- A
12
R
I/O
0
R
- I/O
7
R
SEM
R
INT
R
BUSY
R
M/
S
V
DD
V
SS
Right Port
Names
Chip Enab le
Re ad /Write Enab le
Outp ut Enab le
Ad d re ss
Data Inp ut/Outp ut
Se map ho re Enab le
Inte rrup t Flag
Busy Flag
Maste r o r Slave Se le ct
Po we r (3.3v)
Gro und (0v)
2941 tb l 00
6.42
3
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
L
L
X
R/
W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-7
Hig h-Z
DATA
IN
DATA
OUT
Hig h-Z
De se le cte d : Po we r-Do wn
Write to Me mo ry
Re ad Me mo ry
Outp uts Disab le d
2941 tb l 02
Mode
NOTE:
1. A
0L
— A
12L
≠
A
0R
— A
12R
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
(1)
CE
H
H
L
R/
W
H
↑
X
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-7
DATA
OUT
DATA
IN
____
Mode
Re ad Data in Se map ho re Flag
Writ
e
I/O
0
into Se map ho re Flag
No t Allo we d
2941 tb l 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0
-I/O
7
. These eight semaphores are addressed by A
0
-A
2
.
6.42
4
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Te rminal Vo ltag e
with Re sp e ct
to GND
Te mp e rature
Und e r Bias
Sto rag e
Te mp e rature
DC Outp ut
Curre nt
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Co mme rcial
Ind ustrial
Ambient Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
V
DD
3.3V
+
0.3V
3.3V
+
0.3V
2941 tb l 05
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
o
NOTE:
1. This is the parameter T
A
. This is the "instant on" case temperature.
mA
2941 tb l 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+ 0.3V.
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
Parameter
Sup p ly Vo ltag e
Gro und
Inp ut Hig h Vo ltag e
Inp ut Lo w Vo ltag e
M i n.
3.0
0
2.0
-0.5
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
DD
+0.3
(2)
0.8
Unit
V
V
V
V
2941 tb l 06
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Inp ut Cap acitance
Outp ut Cap acitance
Conditions
V
IN
= 3d V
V
OUT
= 3d V
Max.
9
10
Unit
pF
pF
2941 tb l 07
V
IL
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
DD
+0.3V.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitznce when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V ± 0.3V)
70V05S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Inp ut Le akag e Curre nt
(1)
Outp ut Le akag e Curre nt
Outp ut Lo w Vo ltag e
Outp ut Hig h Vo ltag e
Test Conditions
V
DD
= 3.6V, V
IN
= 0V to V
DD
V
OUT
= 0V to V
DD
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
70V05L
Min.
___
___
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2941 tb l 08
2.4
2.4
NOTE:
1. At V
DD
< 2.0V input leakages are undefined.
6.42
5
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