Quad, 128 Tap, Low Voltage Digitally Controlled
Potentiometer (XDCP™)
ISL23448
The ISL23448 is a volatile, low voltage, low noise, low power,
128 tap, quad digitally controlled potentiometer (DCP) with an
SPI Bus™ interface. It integrates four DCP cores, wiper
switches and control logic on a monolithic CMOS integrated
circuit.
Each digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI bus interface. Each potentiometer has an associated
volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly
written to and read by the user. The contents of the WRi
controls the position of the wiper. When powered on, the wiper
of each DCP will always commence at mid-scale (64 tap
position).
The low voltage, low power consumption, and small package
of the ISL23448 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23448 has a V
LOGIC
pin allowing down to 1.2V bus operation, independent from the
V
CC
value. This allows for low logic levels to be connected
directly to the ISL23448 without passing through a voltage
level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal processing.
Features
• Four potentiometers per package
• 128 resistor taps
• 10kΩ, 50kΩ or 100kΩ total resistance
• SPI serial interface
- No additional level translator for low bus supply
- Daisy Chaining of multiple DCPs
• Power supply
- V
CC
= 1.7V to 5.5V analog power supply
- V
LOGIC
= 1.2V to 5.5V SPI bus/logic power supply
• Maximum supply current without serial bus activity
(standby)
- 5µA @ V
CC
and V
LOGIC
= 5V
- 2µA @ V
CC
and V
LOGIC
= 1.7V
• Shutdown Mode
- Forces the DCP into an end-to-end open circuit and RWi is
connected to RLi internally
- Reduces power consumption by disconnecting the DCP
resistor from the circuit
• Wiper resistance: 70Ω typical @ V
CC
= 3.3V
• Power-on preset to mid-scale (64 tap position)
• Extended industrial temperature range: -40
°
C to +125
°
C
• 20 Ld TSSOP or 20 Ld QFN packages
• Pb-free (RoHS compliant)
Applications
• Power supply margining
• Trimming sensor circuits
• Gain adjustment in battery powered instruments
• RF power amplifier bias compensation
10000
V
REF
8000
RESISTANCE (Ω)
6000
RH1
-
V
REF_M
4000
1 DCP
OF
ISL23448
RW1
+
ISL28114
2000
RL1
0
0
32
64
TAP POSITION (DECIMAL)
96
128
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10kΩ DCP
FIGURE 2. V
REF
ADJUSTMENT
August 19, 2011
FN7905.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners
ISL23448
Block Diagram
V
LOGIC
V
CC
RH0
WR0
VOLATILE
REGISTER
WR1
VOLATILE
REGISTER
WR2
VOLATILE
REGISTER
WR3
VOLATILE
REGISTER
SDI
SDO
SCK
CS
I/O
BLOCK
LEVEL
SHIFTER
RW0
RL0
RH1
RW1
RL1
RH2
RW2
RL2
RH3
RW3
RL3
POWER UP
INTERFACE
CONTROL
AND
STATUS
LOGIC
GND
Pin Configurations
RL0
RW0
V
CC
RH0
RL1
RW1
RH1
GND
V
LOGIC
1
2
3
4
5
6
7
8
9
ISL23448
(20 LD TSSOP)
TOP VIEW
20 RL3
19 RW3
18 RH3
17 RL2
16 RW2
15 RH2
14 SCK
13 SDO
12 GND
11 CS
Pin Descriptions
TSSOP
1
2
3
4
5
6
7
8, 12
9
10
11
13
14
6
16
15
14
13
12
11
RH3
RL2
RW2
RH2
SCK
SDO
QFN
19
20
1
2
3
4
5
6, 10
7
8
9
11
12
13
14
15
16
17
18
SYMBOL
RL0
RW0
V
CC
RH0
RL1
RW1
RH1
GND
V
LOGIC
SDI
CS
SDO
SCK
RH2
RW2
RL2
RH3
RW3
RL3
DESCRIPTION
DCP0 “low” terminal
DCP0 wiper terminal
Analog power supply.
Range 1.7V to 5.5V
DCP0 “high” terminal
DCP1 “low” terminal
DCP1 wiper terminal
DCP1 “high” terminal
Ground pin
SPI bus/logic supply
Range 1.2V to 5.5V
Logic Pin - Serial bus data input
Logic Pin - Active low chip select
Logic Pin - Serial bus data output
(configurable)
Logic Pin - Serial bus clock input
DCP2 “high” terminal
DCP2 wiper terminal
DCP2 “low” terminal
DCP3 “high” terminal
DCP3 wiper terminal
DCP3 “low” terminal
SDI 10
ISL23448
(20 LD QFN)
TOP VIEW
RW0
RW3
RL0
RL3
20
V
CC
RH0
RL1
RW1
RH1
GND
1
2
3
4
5
6
7
V
LOGIC
19
18
17
15
16
17
18
19
20
8
SDI
9
CS
10
GND
2
FN7905.0
August 19, 2011
ISL23448
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL23448TFVZ
ISL23448UFVZ
ISL23448WFVZ
ISL23448TFRZ
ISL23448UFRZ
ISL23448WFRZ
NOTES:
1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL23448.
For more information on MSL please see techbrief
TB363.
PART MARKING
23448 TFVZ
23448 UFVZ
23448 WFVZ
448T
448U
448W
RESISTANCE
OPTION
(kΩ)
100
50
10
100
50
10
TEMP RANGE
(°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
PACKAGE
(Pb-free)
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP
20 Ld 3x4 QFN
20 Ld 3x4 QFN
20 Ld 3x4 QFN
PKG.
DWG. #
M20.173
M20.173
M20.173
L20.3x4
L20.3x4
L20.3x4
3
FN7905.0
August 19, 2011
ISL23448
Absolute Maximum Ratings
Supply Voltage Range
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
V
LOGIC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Wiper Current I
W
(10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 6kV
CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
20 Ld TSSOP Package (Notes 4, 7) . . . . . .
85
33
20 Ld QFN Package (Notes 5, 6) . . . . . . . .
40
4
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
V
CC
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
V
LOGIC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V
DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to V
CC
Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
5.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379
6. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For
θ
JC
, the “case temp” location is taken at the package top center.
Analog Specifications
SYMBOL
R
TOTAL
V
CC
= 2.7V to 5.5V, V
LOGIC
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER
RH to RL Resistance
W option
U option
T option
RH to RL Resistance Tolerance
End-to-End Temperature Coefficient
W option
U option
T option
V
RH
, V
RL
R
W
DCP Terminal Voltage
Wiper Resistance
V
RH
or V
RL
to GND
RH - floating, V
RL
= 0V, force I
W
current to the wiper,
I
W
= (V
CC
- V
RL
)/R
TOTAL,
V
CC
= 2.7V to 5.5V
V
CC
= 1.7V
C
H
/C
L
/C
W
Terminal Capacitance
I
LkgDCP
Noise
Leakage on DCP Pins
Resistor Noise Density
See “DCP Macro Model” on page 8
Voltage at pin from GND to V
CC
Wiper at middle point, W option
Wiper at middle point, U option
Wiper at middle point, T option
Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point
PSRR
Power Supply Reject Ratio
Wiper output change if V
CC
change ±10%; wiper at
middle point
-0.4
0
70
-20
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
10
50
100
±2
125
65
45
V
CC
200
+20
MAX
(Note 20)
UNITS
kΩ
kΩ
kΩ
%
ppm/°C
ppm/°C
ppm/°C
V
Ω
580
32/32/32
< 0.1
16
49
61
-65
-75
0.4
Ω
pF
µA
nV/√Hz
nV/√Hz
nV/√Hz
dB
dB
4
FN7905.0
August 19, 2011
ISL23448
Analog Specifications
SYMBOL
V
CC
= 2.7V to 5.5V, V
LOGIC
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
(Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
VOLTAGE DIVIDER MODE (0V @ RL; V
CC
@ RH; measured at RW, unloaded)
INL
Integral Non-linearity, Guaranteed
(Note 13) Monotonic
W option
U, T option
DNL
Differential Non-linearity, Guaranteed
(Note 12) Monotonic
W option
U, T option
FSerror Full-scale Error
(Note 11)
W option
U, T option
ZSerror Zero-scale Error
(Note 10)
W option
U, T option
Vmatch DCP to DCP Matching
(Note 22)
TC
V
Ratiometric Temperature Coefficient
(Note 14)
DCPs at same tap position, same voltage at all RH
terminals, and same voltage at all RL terminals
W option, Wiper Register set to 40 hex
U option, Wiper Register set to 40 hex
T option, Wiper Register set to 40 hex
t
LS_Settling
Large Signal Wiper Settling Time
f
cutoff
-3dB Cutoff Frequency
From code 0 to 7F hex, measured from 0 to 1LSB
settling of the wiper
Wiper at middle point W option
Wiper at middle point U option
Wiper at middle point T option
-0.5
-0.5
-0.5
-0.5
-3
-1.5
0
0
-2
±0.15
±0.15
±0.15
±0.15
-1.5
-0.9
1.5
0.9
±0.5
8
4
2.3
300
1200
250
120
+1.0
+0.5
+0.5
+0.5
0
0
3
1.5
2
LSB
(Note 9)
LSB
(Note 9)
LSB
(Note 9)
LSB
(Note 9)
LSB
(Note 9)
LSB
(Note 9)
LSB
(Note 9)
LSB
(Note 9)
LSB
(Note 9)
ppm/°C
ppm/°C
ppm/°C
ns
kHz
kHz
kHz
RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)
R
INL
Integral Non-linearity, Guaranteed
(Note 18) Monotonic
W option; V
CC
= 2.7V to 5.5V
W option; V
CC
= 1.7V
U, T option; V
CC
= 2.7V to 5.5V
U, T option; V
CC
= 1.7V
R
DNL
Differential Non-linearity, Guaranteed
(Note 17) Monotonic
W option; V
CC
= 2.7V to 5.5V
W option; V
CC
= 1.7V
U, T option; V
CC
= 2.7V to 5.5V
U, T option; V
CC
= 1.7V
-0.5
-0.5
-0.5
-1.0
±0.5
4
±0.15
1
±0.15
±0.4
±0.15
±0.4
+0.5
+0.5
+0.5
+1.0
MI
(Note 15)
MI
(Note 15)
MI
(Note 15)
MI
(Note 15)
MI
(Note 15)
MI
(Note 15)
MI
(Note 15)
MI
(Note 15)
5
FN7905.0
August 19, 2011
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