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CY62156ESL-45BVXIT

产品描述SRAM 8Mb 45ns 512K x 16 Low Power SRAM
产品类别存储   
文件大小388KB,共16页
制造商Cypress(赛普拉斯)
标准
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CY62156ESL-45BVXIT概述

SRAM 8Mb 45ns 512K x 16 Low Power SRAM

CY62156ESL-45BVXIT规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
Cypress(赛普拉斯)
产品种类
Product Category
SRAM
RoHSDetails
Memory Size8 Mbit
Organization512 k x 16
Access Time45 ns
接口类型
Interface Type
Parallel
电源电压-最大
Supply Voltage - Max
5.5 V
电源电压-最小
Supply Voltage - Min
2.2 V
Supply Current - Max25 mA
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
VFBGA-48
系列
Packaging
Reel
Memory TypeSDR
Moisture SensitiveYes
工厂包装数量
Factory Pack Quantity
2000
单位重量
Unit Weight
0.007873 oz

文档预览

下载PDF文档
CY62156ESL MoBL
®
8-Mbit (512 K × 16) Static RAM
8-Mbit (512 K × 16) Static RAM
Features
High Speed: 45 ns
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
Ultra Low Standby Power
Typical standby current: 2
A
Maximum standby current: 8
A
Ultra Low Active Power
Typical active current: 1.8 mA at f = 1 MHz
Easy Memory Expansion with CE
1
, CE
2
, and OE Features
Automatic Power Down when Deselected
CMOS for Optimum Speed and Power
Available in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) packages
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
in standby mode when deselected (CE
1
HIGH or CE
2
LOW). The
input or output pins (I/O
0
through I/O
15
) are placed in a high
impedance state when the device is deselected (CE
1
HIGH or
CE
2
LOW), the outputs are disabled (OE HIGH), Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or
a write operation is active (CE
1
LOW, CE
2
HIGH and WE LOW).
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is
written into the location specified on the address pins (A
0
through
A
18
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See the
Truth Table on page
11
for a complete description of read and write modes.
For a complete list of related documentation,
click here.
Functional Description
The CY62156ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL
®
) in portable
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
512 K × 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
11
A
12
A
13
A
15
A
17
A
14
A
16
A
18
Cypress Semiconductor Corporation
Document Number: 001-54995 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised November 28, 2014
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