STD5N95K3, STF5N95K3, STP5N95K3,
STU5N95K3
N-channel 950 V, 3
Ω
typ., 4 A Zener-protected SuperMESH3™
Power MOSFET in DPAK, TO-220FP, TO-220 and IPAK packages
Datasheet
−
production data
TAB
Features
3
1
Order codes
3
1
2
V
DS
R
DS(on)
max
I
D
P
TOT
90 W
25 W
90 W
90 W
DPAK
TO-220FP
TAB
STD5N95K3
STF5N95K3
STP5N95K3
STU5N95K3
950 V
3.5
Ω
4A
TAB
3
1
2
•
100% avalanche tested
3
2
1
•
Extremely large avalanche performance
•
Gate charge minimized
•
Very low intrinsic capacitances
•
Zener-protected
TO-220
Figure 1. Internal schematic diagram
D(2, TAB)
Applications
•
Switching applications
G(1)
Description
These SuperMESH3™ Power MOSFETs are the
result of improvements applied to
STMicroelectronics’ SuperMESH™ technology,
combined with a new optimized vertical structure.
These devices boast an extremely low on-
resistance, superior dynamic performance and
high avalanche capability, rendering them suitable
for the most demanding applications.
S(3)
AM01476v1
Table 1. Device summary
Order codes
STD5N95K3
STF5N95K3
5N95K3
STP5N95K3
STU5N95K3
TO-220
IPAK
Tube
Marking
Package
DPAK
TO-220FP
Packaging
Tape and reel
May 2013
This is information on a product in full production.
DocID15696 Rev 3
1/23
www.st.com
23
Contents
STD5N95K3, STF5N95K3, STP5N95K3, STU5N95K3
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
6
Test circuits
.............................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
DocID15696 Rev 3
STD5N95K3, STF5N95K3, STP5N95K3, STU5N95K3
Electrical ratings
1
Electrical ratings
Table 2. Absolute maximum ratings
Value
Symbol
V
GS
I
D
I
D
I
DM (2)
P
TOT
I
AR
E
AS
dv/dt
(3)
V
ISO
T
J
T
stg
Parameter
DPAK TO-220FP TO-220 IPAK
Gate- source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Avalanche current, repetitive or not-
repetitive (pulse width limited by T
J
max)
Single pulse avalanche energy
(starting T
J
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Peak diode recovery voltage slope
Insulation withstand voltage (RMS) from all
three leads to external heat sink
(t = 1 s,T
C
= 25 °C)
Operating junction temperature
Storage temperature
2500
4
3
16
90
4
(1)
3
(1)
16
(1)
25
4
100
5
±30
4
3
16
90
V
A
A
A
W
A
mJ
V/ns
V
Unit
-55 to 150
°C
1. Limited by maximum junction temperature
2. Pulse width limited by safe operating area
3. I
SD
≤
4 A, di/dt
≤
100 A/µs, peak V
DS
≤
V
(BR)DSS
Table 3. Thermal data
Value
Symbol
R
thj-case
R
thj-amb
Parameter
DPAK TO-220FP TO-220 IPAK
Thermal resistance junction-case max
Thermal resistance junction-ambient max
50
1.39
5
62.5
1.39
100
°C/W
°C/W
°C/W
Unit
R
thj-pcb(1)
Thermal resistance junction-pcb max
1. When mounted on 1inch² FR-4 board, 2 oz Cu
DocID15696 Rev 3
3/23
Electrical characteristics
STD5N95K3, STF5N95K3, STP5N95K3, STU5N95K3
2
Electrical characteristics
(Tcase =25 °C unless otherwise specified)
Table 4. On /off states
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter
Drain-source
breakdown voltage
Test conditions
I
D
= 1 mA, V
GS
= 0
Min.
950
1
50
±10
3
4
3
5
3.5
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
Zero gate voltage
V
DS
= 950 V
drain current (V
GS
= 0) V
DS
= 950 V, T
C
=125 °C
Gate-body leakage
current (V
DS
= 0)
V
GS
= ± 20 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 100 µA
Static drain-source on-
V
GS
= 10 V, I
D
= 2 A
resistance
Table 5. Dynamic
Symbol
C
iss
C
oss
C
rss
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent
capacitance time
related
Equivalent
capacitance energy
related
Gate input resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0
Test conditions
Min.
-
-
-
Typ.
460
38
1
Max.
-
-
-
Unit
pF
pF
pF
C
o(tr)
(1)
V
DS
= 0 to 760 V, V
GS
= 0
-
970
-
pF
C
o(er)
R
g
Q
g
(2)
V
DS
= 0 to 760 V, V
GS
= 0
f=1 MHz , I
D
= 0
V
DD
= 760 V, I
D
= 4 A,
V
GS
= 10 V
(see Figure 20)
-
-
-
-
-
15
5.5
19
4.7
12
-
-
-
-
-
pF
Ω
nC
nC
nC
Q
gs
Q
gd
1. Time related is defined as a constant equivalent capacitance giving the same charging time as C
oss
when
V
DS
increases from 0 to 80% V
DSS
2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as C
oss
when V
DS
increases from 0 to 80% V
DSS
4/23
DocID15696 Rev 3
STD5N95K3, STF5N95K3, STP5N95K3, STU5N95K3
Electrical characteristics
Table 6. Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
V
DD
= 475 V, I
D
= 2 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
(see Figure 19)
Test conditions
Min.
-
-
-
-
Typ.
17
7
32
18
Max. Unit
-
-
-
-
ns
ns
ns
ns
Table 7. Source drain diode
Symbol
I
SD
I
SDM (1)
V
SD (2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 4 A, V
GS
= 0
I
SD
= 4 A, di/dt = 100 A/µs
V
DD
= 60 V
(see Figure 21)
I
SD
= 4 A, di/dt = 100 A/µs
V
DD
= 60 V T
J
= 150 °C
(see Figure 21)
Test conditions
Min. Typ. Max. Unit
-
-
-
-
-
-
-
-
-
410
3.5
17
516
4.1
16
4
16
1.6
A
A
V
ns
µC
A
ns
µC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 8. Gate-source Zener diode
Symbol
V
(BR)GSO
Parameter
Gate-source breakdown
voltage
Test conditions
I
GS
= ± 1 mA, I
D
=0
Min.
30
Typ.
-
Max. Unit
-
V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
DocID15696 Rev 3
5/23
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