PFS7323-7329
HiperPFS-2
Family
High Power PFC Controller with Integrated
High-Voltage MOSFET and Qspeed
™
Diode
Key Benefits
•
Output Power Table
eSIP-16 Package
Maximum Continuous
Output Power Rating at
90 VAC (in Full Mode)
110 W
130 W
185 W
230 W
290 W
350 W
380 W
Peak Output Power Rating
Full Mode
(R = 24.9 kW)
120 W
150 W
205 W
260 W
320 W
385 W
425 W
•
•
•
•
•
Highly integrated for smallest boost PFC form factor
•
Integrated controller and MOSFET in all package options
•
Ultra-low reverse recovery loss diode (Qspeed) included in
extended eSIP™ package option
•
Lossless internal current sense reduces component count
and system losses
•
EN61000-3-2 Class C and D compliant
Packaging optimized for high volume production
•
Exposed pad connected to GROUND pin (CoolPAD)
•
Eliminates insulating pad/heat-spreader
Enhanced features
•
Programmable power good (PG) signal
•
User selectable power limit: Enables device swapping in a
given design to optimize efficiency/cost
•
Integrated non-linear amplifier for fast output OV and UV
protection
High efficiency and power factor across load range
•
>95% efficiency from 10% load to full load
•
<200 mW no-load consumption at 230 VAC in remote off-state
•
Light load PF >0.9 at 20% load on optimized designs >200 W
•
PF >0.95 at 50% load
•
Enables 80+ Platinum designs
Frequency adjusted over line voltage and each line cycle
•
Spread-spectrum across >60 kHz window simplifies EMI
filtering requirements
•
Lower boost inductance
Provides up to 425 W peak output power
•
>425 W peak power in power limit voltage regulation mode
Product
PFS7323L
PFS7324L
PFS7325L/H
PFS7326H
PFS7327H
PFS7328H
PFS7329H
Table 1.
Output Power Table (See Table 2 on page 11 for Maximum Continuous
Output Power Ratings.)
•
•
Protection features include: UV, OV, OTP, brown-in/out,
cycle-by-cycle current limit and power limiting for overload
protection
Halogen free and RoHS compliant
•
•
•
•
Applications
•
PC
•
Printer
•
LCD TV
•
Video game consoles
High-power adaptors
High-power LED lighting
Industrial and appliance
Generic PFC converters
D
K
+
PG
VCC
CONTROL
FB
C
PGT
S
V
G
R
VCC
AC
IN
HiperPFS-2
DC
OUT
Figure 1.
Typical Application Schematic.
PI-6691-050313
www.power.com
June 2015
This Product is Covered by Patents and/or Pending Patent Applications.
PFS7323-7329
Description
The HiperPFS™-2 device family members reach a very high level
of integration including a continuous conduction mode (CCM)
boost PFC controller, gate driver, ultra-low reverse recovery
(Qspeed) diode (eSIP™ package options) and high-voltage
power MOSFET in a single, low-profile CoolPAD (GROUND pin
connected) power package that is able to provide near unity
input power factor. The HiperPFS-2 devices eliminate the PFC
converter’s need for external current sense resistors, the power
loss associated with those components, and leverages an
innovative control technique that adjusts the switching frequency
over output load, input line voltage, and even input line cycle.
This control technique is designed to maximize efficiency over
the entire load range of the converter, particularly at light loads.
Additionally, this control technique significantly minimizes the EMI
filtering requirements due to its wide bandwidth spread spectrum
effect. The HiperPFS-2 also features an integrated non-linear
amplifier for enhanced load transient response, a user
programmable power good (PG) signal as well as user selectable
power limit functionality. HiperPFS-2 includes Power Integrations’
standard set of comprehensive protection features, such as
integrated soft-start, UV, OV, brown-in/out, and hysteretic
thermal shutdown. HiperPFS-2 also provides cycle-by-cycle
current limit for the power MOSFET, power limiting of the output
for overload protection, and pin-to-pin short-circuit protection.
HiperPFS-2’s innovative variable frequency continuous
conduction mode of operation (VF-CCM) minimizes switching
losses by maintaining a low average switching frequency, while
also varying the switching frequency in order to suppress EMI,
the traditional challenge with continuous conduction mode
solutions. Systems using HiperPFS-2 typically reduce the total X
and Y capacitance requirements of the converter, the inductance
of both the boost choke and EMI noise suppression chokes,
reducing overall system size and cost. Additionally, compared
with designs that use discrete MOSFETs and controllers,
HiperPFS-2 devices dramatically reduce component count and
board footprint while simplifying system design and enhancing
reliability. The innovative variable frequency, continuous
conduction mode controller enables the HiperPFS-2 to realize all
of the benefits of continuous conduction mode operation while
leveraging low-cost, small, simple EMI filters.
Many regions mandate high power factor for many electronic
products with high power requirements. These rules are
combined with numerous application-specific standards that
require high power supply efficiency across the entire load range,
from full load to as low as 10% load. High efficiency at light load
is a challenge for traditional PFC approaches in which fixed
MOSFET switching frequencies cause fixed switching losses on
each cycle, even at light loads. Besides featuring relatively flat
efficiency across the load range, HiperPFS-2 also enables higher
power factor at light loads. HiperPFS-2 simplifies compliance
with new and emerging energy-efficiency standards over a broad
market space in applications such as PCs, LCD TVs, notebooks,
appliances, pumps, motors, fans, printers, and LED lighting.
HiperPFS-2 advanced power packaging technology and high
efficiency simplifies the complexity of mounting the package and
thermal management, while providing very high power capabilities
in a single compact package; these devices are suitable for PFC
applications from 75 W to 425 W.
Product Highlights
Protected Power Factor Correction Solution
•
Incorporates high-voltage power MOSFET, ultra-low reverse
recovery loss Qspeed diode, controller, and gate driver
•
EN61000-3-2 Class D and Class C compliance
•
Integrated protection features reduce external component count
•
Accurate built-in brown-in/out protection
•
Accurate built-in undervoltage (UV) protection
•
Accurate built-in overvoltage (OV) protection
•
Hysteretic thermal shutdown (OTP)
•
Internal power limiting function for overload protection
•
Cycle-by-cycle power switch current limit
•
Internal non-linear amplifier for enhanced load transient
response
•
No external current sense required
•
Provides ‘lossless’ internal sensing via sense-FET
•
Reduces component count and system losses
•
Minimizes high current gate drive loop area
•
Minimizes output overshoot and stresses during start-up
•
Integrated power limit and frequency soft-start
•
Improved dynamic response
•
Input line feed-forward gain adjustment for constant loop
gain across entire input voltage range
•
Eliminates up to 40 discrete components for higher reliability
and lower cost
Intelligent Solution for High Efficiency and Low EMI
•
Continuous conduction mode PFC uses novel constant volt/
amp-second control engine
•
High efficiency across load
•
High power factor across load
•
Low cost EMI filter
•
Frequency sliding technique for light load efficiency improvements
•
>95% efficiency from 10% load to full load at nominal input
voltages
•
Variable switching frequency to simplify EMI filter design
•
Varies over line input voltage to maximize efficiency and
minimize EMI filter requirements
•
Varies with input line cycle voltage by >60 kHz to maximize
spread spectrum effect
Advanced Package for High Power Applications
•
Up to 425 W peak output power capability in a highly
compact package
•
Simple adhesive or clip mounting to heat sink
•
No insulation pad required and can be directly connected to
heat sink
•
Staggered pin arrangement for simple routing of board traces
and high-voltage creepage requirements
•
Single package solution for PFC converter reduces assembly
costs and layout size
2
Rev. D 06/15
www.power.com
PFS7323-7329
Pin Functional Description
VOLTAGE MONITOR (V) Pin:
The VOLTAGE MONITOR pin is tied to the rectified high-voltage
DC rail through a large resistor (4 MW
±1%)
to minimize power
dissipation and standby power consumption. Modifying this
resistor value affects peak power limit, brown-in/out thresholds
and will degrade input current quality (reduce power factor and
increase THD). A small ceramic capacitor (22 nF) is required
from the VOLTAGE MONITOR pin to SIGNAL GROUND pin to
bypass any switching noise present on the rectified DC bus.
This pin also features brown-in/out detection thresholds.
REFERENCE (R) Pin:
This pin is connected to an external precision resistor and is used for
an internal current reference source in the controller. The external
resistor is tied between the REFERENCE and SIGNAL GROUND
pins. The REFERENCE pin only has two valid resistor values to
select ‘Full’ (24.9 kW
±1%)
and ‘Efficiency’ (49.9 kW
±1%)
power
modes. A precision resistor with the values specified above must
be selected since this sets the internal current reference for the
controller. Other values beyond what is specified may adversely
effect the operation of the device. A bypass capacitor is also
recommended across the REFERENCE pin resistor to the SIGNAL
GROUND pin. For ‘Full’ power mode (24.9 kW) a capacitor
value of 470 pf and 1 nF for the ‘Efficiency’ mode with 49.9 kW.
SIGNAL GROUND (G) Pin:
Discrete components used in the feedback circuit, including
loop compensation, decoupling capacitors for the supply (VCC)
and line-sense (V) must be referenced to the SIGNAL GROUND
pin. The SIGNAL GROUND pin is also connected to the tab of
the device.
The SIGNAL GROUND pin must not be tied to
the SOURCE pin.
COMPENSATION (C) Pin:
This pin is used for loop compensation and voltage feedback.
The COMPENSATION pin is a high input-impedance reference
terminal that connects to the main voltage regulation feedback
resistor divider network. This pin also connects to the loop
compensation components comprising of a series RC network.
A 22 nF capacitor is also required between the COMPENSATION
and SIGNAL GROUND pins; this capacitor must be placed very
close to the device on the PCB to bypass any switching noise.
FEEDBACK (FB) Pin:
This pin is connected to the main voltage regulation feedback
resistor divider network and is used for fast over and under-
voltage protection. This pin also detects the presence of the
main voltage divider network at start-up.
POWER GOOD THRESHOLD (PGT) Pin:
This pin is used to program the output voltage threshold where
the PG signal becomes ‘high-impedance’ representing the PFC
stage falling out of regulation. The low threshold for the PG
signal is programmed with a resistor between the POWER
GOOD THRESHOLD and SIGNAL GROUND pins.
POWER GOOD (PG) Pin:
This pin is an open-drain connection that indicates that the
output voltage is in regulation. At start-up, once the FEEDBACK
pin voltage has risen to ~95% of the set output voltage, the
POWER GOOD pin is pulled low. After start-up the output
voltage threshold at which the PG signal becomes high-
impedance depends on the threshold programmed by the
POWER GOOD THRESHOLD pin resistor.
BIAS POWER (VCC) Pin:
This is a 10.2-13 VDC bias supply used to power the IC. The
bias voltage must be externally clamped to prevent the BIAS
POWER pin from exceeding 15 VDC.
SOURCE (S) Pin:
This pin is the source connection of the power switch.
DRAIN (D) Pin:
This is the drain connection of the internal power switch.
BOOST DIODE CATHODE (K) Pin: (eSIP-16 package only)
This is the cathode connection of the internal Qspeed Diode.
H Package (eSIP-16D)
(Front View)
Pin 1 I.D.
1
V
G
3 4 5 6 7 8 9 1011 13 14 16
S
S
VCC
PGT
PG
FB
C
G
R
NC
D
K
G
Exposed Metal (Both H and L
Packages) (On Package Edge)
Internally Connected to G Pin
Exposed Pad (Backside)
Internally Connected to
GROUND (G) Pin
H Package
(eSIP-16D)
(Back View)
16 14 13 1110 9 8 7 6 5 4 3
K
1
V
1
V
R
G
C
FB
PG
PGT
VCC
S
S
6
FB
D
NC
4
G
L Package (eSIP-16G)
(Front View)
Pin 1 I.D.
8 10
PGT
S
13
D
16
K
Exposed Pad
(Backside)
Not Shown
3
R
5
C
7
9
11
S
14
NC
PI-6789-022213
PG
VCC
Figure 2.
Pin Configuration.
3
www.power.com
Rev. D 06/15
PFS7323-7329
DRAIN (D)
BOOST DIODE CATHODE (K)
VOLTAGE MONITOR (V)
I
V
INPUT
LINE INTERFACE
Peak
Detector
Input UV
(I
UV+
/I
UV-
)
I
VPK
M
ON
FB
OV
M
OFF
(I
REF
- I
V
)
~(V
O-
V
IN
)
C
INT
I
V
I
REF
INTERNAL
SUPPLY
SOFT-
START
BIAS POWER (VCC)
+
-
V
CC+
C
UV
/
FB
OFF
/
VREF
FBC
OV
C
OFF
I
OCP
V
PG(H)
I
PGT
FBC
UV
REFERENCE
(R)
REFERENCE
AND BAND GAP
Feedback-OVP/OFF
Comparator
FEEDBACK/
COMPENSATION Pin
OV/UV
TIMER
SUPERVISOR
Power
MOSFET
senseFET
VCC
Latch
V
OFF
is a function of the error-voltage
(V
E
) and is used to reduce the
average operating frequency as a
function of output power
V
OFF
+
-
FB
ON
/
FB
OFF
V
FB
FEEDBACK
(FB)
V
CC
+
Comparator
-
+
V
OFF
V
E
Frequency
Slide
V
E
+
-
I
S
Transconductance
Error-Ampli er
Internal
1 kHz Filter
Reference
V
REF
+
-
I
VPK
FB
GM
-
FBC
OV
+
-
+
-
Buffer and
De-Glitch Filter
+
LEB
FB
GM
-
FBC
UV
COMPENSATION
(C)
Comparator
I
OCP
+
-
OCP
m
ON
is the switch
current sense scale
factor which is a function
of the peak input voltage
C
INT
P
ON
×
M
ON
×
I
S
INPUT UV
OTP SOA
C-UV/OFF
Comparator
+
C
UV
/C
OFF
V
FB
V
CC
V
PG(H)
I
PGT
POWER GOOD
THRESHOLD
(PGT)
+
POWER GOOD
(PG)
SOURCE (S)
GROUND (G)
PI-6697-050312
Figure 3.
Functional Block Diagram.
Functional Description
The HiperPFS-2 is a variable switching frequency boost PFC
solution. More specifically, it employs a constant amp-second
on-time and constant volt-second off-time control algorithm.
This algorithm is used to regulate the output voltage and shape
the input current to comply with regulatory harmonic current
limits (high power factor). Integrating the switch current and
controlling it to have a constant amp-sec product over the
on-time of the switch allows the average input current to follow
the input voltage. Integrating the difference between the output
and input voltage maintains a constant volt-second balance
dictated by the electro-magnetic properties of the boost
inductor and thus regulates the output voltage and power.
More specifically, the control technique sets constant volt-
seconds for the off-time (t
OFF
). The off-time is controlled such
that:
^
V
O
-
V
IN
h
#
t
OFF
=
K
1
(1)
Since the volt-seconds during the on-time must equal the
volt-seconds during the off-time, to maintain flux equilibrium in
the PFC choke, the on-time (t
ON
) is controlled such that:
V
IN
#
t
ON
=
K
1
(2)
The controller also sets a constant value of charge during each
on-cycle of the power MOSFET. The charge per cycle is varied
gradually over many switching cycles in response to load
changes so it can be regarded as substantially constant for a
half line cycle. With this constant charge (or amp-second)
control, the following relationship is therefore also true:
I
IN
#
t
ON
=
K
2
Substituting t
ON
from (2) into (3) gives:
(3)
I
IN
=
V
IN
#
K
2
K
1
(4)
4
Rev. D 06/15
www.power.com
PFS7323-7329
The relationship of (4) demonstrates that by controlling a constant
amp-second on-time and constant volt-second off-time, the
input current I
IN
is proportional to the input voltage V
IN
, therefore
providing the fundamental requirement of power factor correction.
This control produces a continuous mode power switch current
waveform that varies both in frequency and peak current value
across a line half-cycle to produce an input current proportional
to the input voltage.
PI-5335-111610
the VOLTAGE MONITOR pin resistor also affects power limit of
the device.
This characteristic is optimized to maintain a relatively constant
internal error-voltage level at full load from an input line of 100 to
230 VAC input.
Beyond the specified peak power rating of the device, the
internal power limit feature will regulate the output voltage below
the set regulation threshold as a function of output overload
beyond the peak power rating. Figure 5 illustrates the typical
regulation characteristic as function of load.
Normalized to Set Output Voltage
Regulation Threshold
PI-6216-113010
V
E
Latch
RESET
V
OFF
Latch
SET
Gate
Drive (Q)
Maximum
ON-time
Minimum
OFF-time
Timing
Supervisor
(V
OUT
-V
IN
)dt
I
S
dt
1.2
1
0.8
0.6
0.4
0.2
0
Figure 4.
Idealized Converter Waveforms.
Control Engine
The controller features a low bandwidth error-amplifier which
connects its non-inverting terminal to an internal voltage
reference of 6 V. The inverting terminal of the error-amplifier is
available on the external CONTROL pin which connects to the
loop compensation and voltage divider network to regulate the
output voltage. The FEEDBACK pin connects directly to the
divider network for fast transient load response.
The internal sense-FET switch current is integrated and scaled
by the input voltage peak detector current sense gain (M
ON
) and
compared with the error-amplifier signal (V
E
) to determine the
cycle on-time. Internally the difference between the input and
output voltage is derived and the resultant is scaled, integrated,
and compared to a voltage reference (V
OFF
) to determine the
cycle off-time. Careful selection of the internal scaling factors
produce input current waveforms with very low distortion and
high power factor.
Line Feed-Forward Scaling Factor (M
ON
)
The VOLTAGE MONITOR (V) pin current is used internally to
derive the peak of the input line voltage which is used to scale
the gain of the current sense signal through the M
ON
variable.
This contribution is required to reduce the dynamic range of the
control feedback signal as well as maintain a constant loop gain
over the operating input line range. This line-sense feed-
forward gain adjustment is proportional to the square of the
peak rectified AC line voltage and is adjusted as a function of
VOLTAGE MONITOR pin current. The line-sense feed-forward
gain is also important in providing a switch power limit over the
input line range. Besides modifying brown- in/out thresholds,
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Normalized to Peak Power Rating
Figure 5.
Typical Normalized Output Voltage Characteristics as Function of
Normalized Peak Load Rating
Below the brown-in threshold (I
UV+
) the power limit is reduced
when the device is operated in the ‘Full’ power mode as shown
in the figure below.
Normalized Minimum Power Limit
PI-6940-013013
1.2
1
0.8
0.6
0.4
0.2
0
70
75
80
85
90
95
100
Input Voltage (VAC)
Figure 6.
Normalized Minimum Power Limit as Function of Input Voltage.
As the input line voltage is reduced toward the brown-out
threshold (I
UV-
) and if the load exceeds the power limit derating
the boost output voltage will drop out of regulation in
accordance to Figure 6.
5
www.power.com
Rev. D 06/15
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