74ACT138
3 TO 8 LINE DECODER (INVERTING)
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT138B
74ACT138M
DESCRIPTION
The 74ACT138 is an advanced high-speed CMOS
3 TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS tecnology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
PIN CONNECTION AND IEC LOGIC SYMBOLS
O
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b
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t(
bs
-O
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
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T&R
74ACT138MTR
74ACT138TTR
April 2001
1/10
74ACT138
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
400
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
Parameter
Value
4.5 to 5.5
0 to V
CC
0 to V
CC
8
1) V
IN
from 0.8V to 2.0V
O
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b
te
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t(
so
b
-O
te
le
r
P
-55 to 125
od
s)
t(
uc
Unit
V
V
V
°C
ns/V
3/10
74ACT138
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Low Level Output
Voltage
4.5
5.5
4.5
5.5
I
I
I
CCT
I
CC
I
OLD
I
OHD
Input Leakage Cur-
rent
Max I
CC
/Input
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
5.5
5.5
5.5
5.5
V
O
= 0.1 V or
V
CC
-0.1V
V
O
= 0.1 V or
V
CC
-0.1V
I
O
=-50
µA
I
O
=-50
µA
I
O
=-24 mA
I
O
=-24 mA
I
O
=50
µA
I
O
=50
µA
I
O
=24 mA
I
O
=24 mA
V
I
= V
CC
or GND
V
I
= V
CC
- 2.1V
V
I
= V
CC
or GND
V
OLD
= 1.65 V max
V
OHD
= 3.85 V min
0.6
4
4.4
5.4
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
± 0.1
T
A
= 25°C
Min.
2.0
2.0
Typ.
1.5
1.5
1.5
1.5
4.49
5.49
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Max.
Value
-40 to 85°C
Min.
2.0
2.0
0.8
0.8
4.4
5.4
3.7
4.7
0.1
Max.
-55 to 125°C
Min.
2.0
2.0
0.8
0.8
V
V
Max.
Unit
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
O
(*) Voltage range is 5.0V ± 0.5V
so
b
t
PLH
t
PHL
Propagation Delay
Time A, B, C to Y
t
PLH
t
PHL
Propagation Delay
Time G1 to Y
t
PLH
t
PHL
Propagation Delay
Time G2A or G2B
to Y
te
le
r
P
uc
od
V
CC
(V)
s)
t(
so
b
-O
Min.
5.0
5.0
5.5
et
l
P
e
Value
od
r
1.5
40
75
-75
±1
s)
t(
uc
0.5
0.5
±1
1.6
80
50
-50
0.1
V
µA
mA
µA
mA
mA
T
A
= 25°C
Typ.
Max.
9.0
8.0
8.5
-40 to 85°C
Min.
Max.
10.0
9.0
10.0
-55 to 125°C
Min.
Max.
10.5
9.5
10.5
Unit
5.0
(*)
5.0
(*)
5.0
(*)
ns
ns
ns
4/10
74ACT138
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
f
IN
= 10MHz
T
A
= 25°C
Min.
Typ.
4
60
Max.
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS
(f=1MHz; 50% duty cycle)
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b
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t(
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-O
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t(
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5/10
FPGA/CPLD
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