IS66WVH16M8ALL/BLL
IS67WVH16M8ALL/BLL
16M
x 8 HyperRAM™
August
2017
Overview
The IS66/67WVH16M8ALL/BLL are integrated memory device
of
128Mbit
Pseudo Static Random Access
Memory using a self-refresh DRAM array organized as
16M
words by 8 bits.
The device is a dual die stack of
two 64Mb die.
The device supports a HyperBus interface, Very Low Signal Count (Address, Command and
data through 8 DQ pins),
Hidden Refresh Operation, and Automotive Temperature Operation, designed
specially for Mobile and
Automotive applications.
Distinctive Characteristics
HyperBus
TM
Low Signal Count Interface
3.0V I/O, 11 bus signals
– Single ended clock (CK)
1.8V I/O, 12 bus signals
– Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
– Bidirectional Data Strobe / Mask
– Output at the start of all transactions to indicate refresh
latency
– Output during read transactions as Read Data Strobe
– Input during write transactions as Write Data Mask
RWDS DCARS Timing
High Performance
Up to 333MB/s
Double-Data Rate (DDR) - two data transfers per clock
166-MHz clock rate (333 MB/s) at 1.8V V
CC
100-MHz clock rate (200 MB/s) at 3.0V V
CC
Sequential burst transactions
Configurable Burst Characteristics
– Wrapped burst lengths:
– 16 bytes (8 clocks)
– 32 bytes (16 clocks)
– 64 bytes (32 clocks)
– 128 bytes (64 clocks)
– Linear burst
– Hybrid option - one wrapped burst followed by linear burst
– Wrapped or linear burst type selected in each transaction
– Configurable output drive strength
Package
– 24-ball FBGA
– During read transactions RWDS is offset by a second
clock, phase shifted from CK
– The Phase Shifted Clock is used to move the RWDS
transition edge within the read data eye
Performance Summary
Read Transaction Timings
Maximum Clock Rate at 1.8V V
CC
/V
CC
Q
Maximum Clock Rate at 3.0V V
CC
/V
CC
Q
Maximum Access Time, (t
ACC
at 166 MHz)
Maximum CS# Access Time to first word at
166 MHz (excluding refresh latency)
166 MHz
100 MHz
36 ns
56 ns
Maximum Current Consumption
Burst Read or Write (linear burst at 166 MHz,
3V)
Burst Read or Write (linear burst at 166 MHz, 1.8V)
Standby (CS# = High, 3V, 105 °C)
Standby (CS# = High, 1.8V, 105 °C)
45
mA
60 mA
600
µA
600
µA
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice.
ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this
device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be
expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated
Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
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IS66WVH16M8ALL/BLL
IS67WVH16M8ALL/BLL
Block Diagram
RWDS
DQ0~DQ7
RWDS
DQ0~DQ7
VssQ
VccQ
64Mb
HyperRAM
(Top Die)
VssQ
VccQ
RESET#
CS#
CK/CK#
(PSC/PSC#)
RESET#
CS#
CK/CK#
Vss
Vcc
Vss
Vcc
(PSC/PSC#)
RWDS
DQ0~DQ7
VssQ
VccQ
64Mb
HyperRAM
(Bottom Die)
RESET#
CS#
CK/CK#
Vss
Vcc
(PSC/PSC#)
Key Diefference between Stacked 128Mb and Monolithic 64Mb
Stacked 128Mb device is different from monolithic based 64Mb in below 6 items.
1.
Configuration Register 0, 1 must be set per each die individually by CA35 (0 or 1).
CA35 (A22) = 0 for bottom die, CA35 (A22) = 1 for top die.
2.
3.
4.
5.
6.
Deep Power Down mode by CR write supports for only 1 die only ( either bottom or top die)
It is selected by CA35 staus when Deep Power Down operation is executed.
Fixed Latency mode only supported (No Variable latency mode)
Table 5.1 ID Register Bit Assignments
When Linear Burst is selected by CA[45], the device cannot advance across to next die.
Input Output Capacitance value will be doubled in stacked 128Mb device, which will impact on
clock to data (strobe) access time of tCKD, tCKDI, tCKDS, tDSV and tID/tIH.
Symbol
tCKD
tCKDI
tCKDS
tDSV
tIS/tIH
Parameter
CK transition to DQ Valid
CK transition to RWDS Valid
CK transition to RWDS Valid
Data Strobe Valid
Input Setup/Hold
1.8V Device
5.5ns 6.5ns
4.6/4.5/4.3ns
5.6/5.5/5.3ns
5.5ns 6.5ns
12.0ns 13.0ns
0.6/0.8/1.0ns
0.9/0.9/1.0ns
3.0V Device
7.0ns 8.0ns
5.2ns 6.2ns
7.0ns 8.0ns
12.0ns 13.0ns
No change (1.0ns)
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IS66WVH16M8ALL/BLL
IS67WVH16M8ALL/BLL
Contents
1.
2.
3.
3.1
3.2
3.3
3.4
3.5
4.
5.
5.1
5.2
6.
6.1
7.
7.1
7.2
8.
9.
9.1
9.2
9.3
9.4
9.5
9.6
General Description.....................................................
4
HyperRAM Product Overview
..................................... 7
HyperRAM Signal Descriptions
.................................. 8
Input/Output Summary................................................... 8
Command/Address Bit Assignments ............................. 9
Read Transactions....................................................... 13
Write Transactions with Initial Latency
(Memory Core Write) ................................................... 14
Write Transactions without Initial Latency
(Register Write)............................................................ 16
Memory Space............................................................
16
Register Space
........................................................... 17
Device Identification Registers..................................... 17
Register Space Access................................................ 18
Interface States
.......................................................... 25
Power Conservation Modes......................................... 25
HyperRAM Connection Descriptions
....................... 27
Other Connectors Summary ........................................ 27
HyperRAM Block Diagram ........................................... 28
Interface States
.......................................................... 29
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Latchup Characteristics ...............................................
Operating Ranges........................................................
DC Characteristics .......................................................
Power-Up Initialization .................................................
Power Down.................................................................
30
30
31
31
32
33
35
9.7
10.
10.1
10.2
10.3
Hardware Reset ............................................................ 36
Timing Specifications.................................................
37
Key to Switching Waveforms ........................................ 37
AC Test Conditions ....................................................... 37
AC Characteristics ........................................................ 38
11. Physical Interface
....................................................... 41
11.1 FBGA 24-Ball 5 x 5 Array Footprint .............................. 41
DDR Center Aligned
Read Strobe Functionality
......................................... 42
12.1 HyperRAM Products with DCARS
Signal Descriptions ....................................................... 42
12.2 HyperRAM Products with DCARS
— FBGA 24-ball, 5x5 Array Footprint ........................... 43
12.3 HyperRAM Memory with DCARS Timing...................... 43
13. Ordering
Rule
Information............
............................ 44
13.1 Ordering Part Number................................................... 45
14.
PACKAGE INFORMATION..............................
............ 47
12.
HyperRAM Device Hardware Interface
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Rev.B2
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IS66WVH16M8ALL/BLL
IS67WVH16M8ALL/BLL
The
ISSI
128-Mbit
HyperRAM
TM
device is a high-speed CMOS, self-refresh Dynamic RAM (DRAM), with a HyperBus interface.
The Random Access Memory (RAM) array uses dynamic cells that require periodic refresh. Refresh control logic within the device
manages the refresh operations on the RAM array when the memory is not being actively read or written by the HyperBus interface
master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the
memory uses static cells that retain data without refresh. Hence, the memory can also be described as Pseudo Static RAM
(PSRAM).
Because the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host not perform
read or write burst transfers that are long enough to block the necessary internal logic refresh operations when they are needed. The
host is required to limit the duration of transactions and allow additional initial access latency, at the beginning of a new transaction,
if the memory indicates a refresh operation is needed.
HyperBus is a low signal count, Double Data Rate (DDR) interface, that achieves high speed read and write throughput. The DDR
protocol transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on HyperBus consists of
a series of 16-bit wide, one clock cycle data transfers at the internal HyperRAM core with two corresponding 8-bit wide, one-half-
clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Ordering Part Number (OPN) device
versions are available for core (V
CC
) and IO buffer (V
CC
Q) supplies of either 1.8V or 3.0V (nominal).
Command, address, and data information is transferred over the eight HyperBus DQ[7:0] signals. The clock is used for information
capture by a HyperBus slave device when receiving command, address, or data on the DQ signals. Command or Address values
are center aligned with clock transitions.
Every transaction begins with the assertion of CS# and Command-Address (CA) signals, followed by the start of clock transitions to
transfer six CA bytes, followed by initial access latency and either read or write data transfers, until CS# is deasserted.
1.
General Description
Figure 1.1
Read Transaction,
Fixed
Latency
Mode
CS#
t
RWR
=Read Write Recovery
CK, CK#
Additional Latency
t
ACC
= Access
4 cycle latency 1
t
DSV
RWDS
4 cycle latency 2
t
CKDS
High = 2x Latency Count
DQ[7:0]
47:40 39:32 31:24 23:16 15:8
7:0
Dn
A
Dn
B
Dn+1
A
Dn+1
B
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Memory drives DQ[7:0]
and RWDS
The Read/Write Data Strobe (RWDS) is a bidirectional signal that indicates:
–
–
–
–
when data will start to transfer from a HyperRAM device to the master device in read transactions (initial read latency)
when data is being transferred from a HyperRAM device to the master device during read transactions (as a source
synchronous read data strobe)
when data may start to transfer from the master device to a HyperRAM device in write transactions (initial write latency)
data masking during write data transfers
During read data transfers, RWDS is a read data strobe with data values edge aligned with the transitions of RWDS.
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IS66WVH16M8ALL/BLL
IS67WVH16M8ALL/BLL
Figure 1.2
Write Transaction, Fixed Latency Mode
CS#
t
RWR
=Read Write Recovery
CK,CK#
4 cycle latency 1
RWDS
DQ[7:0]
High = 2x Latency Count
47:40 39:32 31:24 23:16 15:8
7:0
Dn
A
Dn
B
Dn+1
A
Dn+1
B
Additional Latency
t
ACC
= Access
4 cycle latency 2
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
CK and Data
are center aligned
Host drives DQ[7:0]
and RWDS
During write data transfers, RWDS indicates whether each data byte transfer is masked with RWDS High (invalid and prevented
from changing the byte location in a memory) or not masked with RWDS Low (valid and written to a memory). Data masking may be
used by the host to byte align write data within a memory or to enable merging of multiple non-word aligned writes in a single burst
write. During write transactions, data is center aligned with clock transitions.
Read and write transactions are burst oriented, transferring the next sequential word during each clock cycle. Each individual read
or write transaction can use either a wrapped or linear burst sequence.
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