74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Rev. 2 — 22 November 2012
Product data sheet
1. General description
The 74HC4053-Q100; 74HCT4053-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no. 7A.
The 74HC4053-Q100; 74HCT4053-Q100 is triple 2-channel analog
multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer
has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three
digital select inputs (Sn). With E LOW, one of the two switches is selected
(low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the
high-impedance OFF-state, independent of S1 to S3.
V
CC
and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
The V
CC
to GND ranges are 2.0 V to 10.0 V for 74HC4053-Q100, and 4.5 V to 5.5 V for
74HCT4053-Q100. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between
V
CC
as a positive limit and V
EE
as a negative limit. V
CC
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically
ground).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide analog input voltage range from
5
V to +5 V
Low ON resistance:
80
(typical) at V
CC
V
EE
= 4.5 V
70
(typical) at V
CC
V
EE
= 6.0 V
60
(typical) at V
CC
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
5
V analog signals
Typical ‘break before make’ built-in
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
CDM AEC-Q100-011 revision B exceeds 1000 V
Multiple package options
Nexperia
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC4053D-Q100
74HCT4053D-Q100
74HC4053PW-Q100
74HCT4053PW-Q100
74HC4053BQ-Q100
74HCT4053BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
SOT763-1
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5
3.5
0.85 mm
74HC_HCT4053_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 22 November 2012
2 of 30
Nexperia
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
5. Functional diagram
E
6
V
CC
16
13 1Y1
S1 11
LOGIC
LEVEL
CONVERSION
DECODER
12 1Y0
14 1Z
1 2Y1
S2 10
LOGIC
LEVEL
CONVERSION
2 2Y0
15 2Z
3 3Y1
S3 9
LOGIC
LEVEL
CONVERSION
5 3Y0
4 3Z
8
GND
7
V
EE
001aak341
Fig 1.
Functional diagram
6
11
10
9
S1
S2
S3
1Y0
1Y1
1Z
2Y0
2Y1
2Z
3Y0
3Y1
6
E
3Z
12
13
14
2
1
15
5
3
4
10
15
#
11
14
#
EN
MUX/DMUX
0
×
0
1
0/1
1
12
13
2
1
9
4
#
5
3
001aae126
001aae125
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
©
74HC_HCT4053_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 22 November 2012
3 of 30
Nexperia
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Y
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
Z
V
EE
001aad544
Fig 4.
Schematic diagram (one switch)
6. Pinning information
6.1 Pinning
74HC4053-Q100
74HCT4053-Q100
terminal 1
index area
2Y0
16 V
CC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
9
aaa-003164
74HC4053-Q100
74HCT4053-Q100
2Y1
2Y0
3Y1
3Z
3Y0
E
V
EE
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
S3
9
V
CC(1)
16 V
CC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
3Y1
3Z
3Y0
E
V
EE
1
2Y1
S3
aaa-003165
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 5.
Pin configuration SO16 and TSSOP16
Fig 6.
Pin configuration DHVQFN16
74HC_HCT4053_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 22 November 2012
4 of 30
Nexperia
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
6.2 Pin description
Table 2.
Symbol
E
V
EE
GND
S1, S2, S3
1Y0, 2Y0, 3Y0
1Y1, 2Y1, 3Y1
1Z, 2Z, 3Z
V
CC
Pin description
Pin
6
7
8
11, 10, 9
12, 2, 5
13, 1, 3
14, 15, 4
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
independent input or output
common output or input
supply voltage
7. Functional description
Table 3.
Inputs
E
L
L
H
[1]
Function table
[1]
Channel on
Sn
L
H
X
nY0 to nZ
nY1 to nZ
switches off
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
CC
I
IK
I
SK
I
SW
I
EE
I
CC
I
GND
T
stg
P
tot
P
[1]
Parameter
supply voltage
input clamping current
switch clamping current
switch current
supply current
supply current
ground current
storage temperature
total power dissipation
power dissipation
Conditions
[1]
Min
0.5
-
-
-
-
-
-
65
[2]
Max
+11.0
20
20
25
20
50
50
+150
500
100
Unit
V
mA
mA
mA
mA
mA
mA
C
mW
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
0.5
V or V
SW
> V
CC
+ 0.5 V
0.5
V < V
SW
< V
CC
+ 0.5 V
-
-
per switch
To avoid drawing V
CC
current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no V
CC
current flows out of terminals nYn. In this case, there is
no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed V
CC
or V
EE
.
For SO16 package: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For TSSOP16 package: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 package: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
[2]
74HC_HCT4053_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 22 November 2012
5 of 30
FPGA/CPLD
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