INTEGRATED CIRCUITS
CBTD3257
Quad 1-of-2 multiplexer/demultiplexer
with level shifting
Preliminary data
2002 Sep 09
Philips
Semiconductors
Philips Semiconductors
Preliminary data
Quad 1-of-2 multiplexer/demultiplexer
with level shifting
CBTD3257
FEATURES
•
5
Ω
switch connection between two ports
•
TTL-compatible input levels
•
Designed to be used in level shifting applications
•
Minimal propagation delay through the switch
•
Latch-up protection exceeds 500 mA per JESD78
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
PIN CONFIGURATION
S
1B1
1B2
1A
2B1
2B2
2A
GND
1
2
3
4
5
6
7
8
16 V
CC
15 OE
14 4B1
13 4B2
12 4A
11 3B1
10 3B2
9
3A
DESCRIPTION
The CBTD3257 is a quad 1-of-2 high-speed TTL-compatible
multiplexer/demultiplexer. The low on resistance of the switch allows
inputs to be connected to outputs without adding propagation delay
or generating additional ground bounce noise.
Output Enable (OE) and select-control (S) inputs select the
appropriate B1 and B2 outputs for the A-input data.
Internal diode allows voltage level shifting from 5 V inputs to 3.3 V
outputs.
The CBTD3257 is characterized for operation from –40 to +85
°C.
SA00533
PIN DESCRIPTION
PIN NUMBER
1
2, 3,
5, 6,
10, 11,
13, 14
4, 7, 9, 12
8
15
16
SYMBOL
S
1B1, 1B2,
2B1, 2B2
3B1, 3B2
4B1, 4B2
1A, 2A, 3A, 4A
GND
OE
V
CC
NAME AND FUNCTION
Select-control input
B outputs
A inputs
Ground (0 V)
Output enable
Positive supply voltage
ORDERING INFORMATION
PACKAGES
16-pin plastic SO
16-pin plastic SSOP
16-pin plastic SSOP (QSOP)
16-pin plastic TSSOP
TEMPERATURE RANGE
–40 to 85
°C
–40 to 85
°C
–40 to 85
°C
–40 to 85
°C
ORDER CODE
CBTD3257D
CBTD3257DB
CBTD3257DS
CBTD3257PW
TOPSIDE MARK
CBTD3257D
CD3257
CBD3257
CBD3257
DWG NUMBER
SOT109-1
SOT338-1
SOT519-1
SOT403-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2002 Sep 09
2
Philips Semiconductors
Preliminary data
Quad 1-of-2 multiplexer/demultiplexer
with level shifting
CBTD3257
LOGIC DIAGRAM (positive logic)
1A
4
2
1B1
FUNCTION TABLE
INPUTS
OE
L
3
1B2
S
L
H
X
FUNCTION
A port = B1 port
A port = B2 port
Disconnect
L
H
2A
7
5
2B1
6
2B2
3A
9
11
3B1
10
3B2
4A
12
14
4B1
13
4B2
S
1
OE
15
SA00532
2002 Sep 09
3
Philips Semiconductors
Preliminary data
Quad 1-of-2 multiplexer/demultiplexer
with level shifting
CBTD3257
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
CC
V
I
I
K
T
stg
PARAMETER
DC supply voltage
DC input voltage
2
Continuous channel current
Input clamp current
Storage temperature range
V
I/O
< 0
CONDITIONS
RATING
–0.5 to +7.0
–0.5 to +7.0
128
–50
–65 to +150
UNIT
V
V
mA
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IH
V
IL
T
amb
DC supply voltage
High-level input voltage
Low-level Input voltage
Operating free-air temperature range
PARAMETER
LIMITS
MIN
4.5
2.0
—
–40
MAX
5.5
—
0.8
+85
UNIT
V
V
V
°C
NOTE:
1. All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation.
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
V
IK
V
P
I
I
I
CC
∆I
CC
C
I
C
IO(OFF)
O(O )
PARAMETER
Input clamp voltage
Pass voltage
Input leakage current
Quiescent supply current
Additional supply current per input pin
2
Control pins
Power-off
Power off leakage current
A port
B port
TEST CONDITIONS
V
CC
= 4.5 V; I
I
= –18 mA
V
I
= V
CC
= 5.5 V; I/O = –100 mA
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 5.5 V; I
O
= 0, V
I
= V
CC
or GND
V
CC
= 5.5 V, one input at 3.4 V,
other inputs at V
CC
or GND
V
I
= 3 V or 0
V
O
= 3 V or 0; OE = V
CC
V
O
= 3 V or 0; OE = V
CC
V
CC
= 4.5 V; V
I
= 0V; I
I
= 64 mA
r
on3
On-resistance
V
CC
= 4.5 V; V
I
= 0V; I
I
= 30 mA
V
CC
= 4.5 V; V
I
= 2.4 V; I
I
= 15 mA
—
—
—
—
—
—
—
—
—
T
amb
= –40 to +85
°C
MIN
—
TYP
1
—
See Figure 1
—
—
—
4.5
12.5
6.5
5
5
16
±1
1.5
2.5
—
—
—
7
7
50
µA
mA
mA
pF
pF
pF
Ω
Ω
Ω
MAX
–1.2
V
UNIT
NOTES:
1. All typical values are at V
CC
= 5 V, T
amb
= 25
°C.
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch.
On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
2002 Sep 09
4
Philips Semiconductors
Preliminary data
Quad 1-of-2 multiplexer/demultiplexer
with level shifting
CBTD3257
AC CHARACTERISTICS
T
amb
= –40 to +85
°C;
C
L
= 50 pF
LIMITS
SYMBOL
t
pd
t
pd
t
en
t
dis
PARAMETER
Propagation delay
1
Propagation delay
Output enable time
to High and Low level
Output disable time
from High and Low level
FROM (INPUT)
A or B
S
OE
S
OE
S
TO
(OUTPUT)
B or A
A
A or B
B
A or B
B
V
CC
= +5.0 V
±0.5
V
MIN
—
1.6
1.8
1.6
2.2
2.0
MAX
0.25
11.0
11.2
10.8
6.0
8.0
ns
ns
ns
ns
ns
ns
UNIT
NOTE:
1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V
3V
1.5 V
INPUT
0V
t
PLH
t
PHL
V
OH
1.5 V
OUTPUT
V
OL
1.5 V
1.5 V
TEST CIRCUIT AND WAVEFORMS
7V
From Output
Under Test
C
L
= 50 pF
500
Ω
S1
Open
GND
500
Ω
Load Circuit
TEST
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
open
7V
open
SA00028
Waveform 1. Input to Output Propagation Delays
DEFINITIONS
Load capacitance includes jig and probe capacitance;
C
L
=
see AC CHARACTERISTICS for value.
3V
Output Control
(Low-level
enabling )
t
PZL
Output
Waveform 1
S1 at 7 V
(see Note)
t
PZH
Output
Waveform 2
S1 at Open
(see Note)
1.5 V
1.5 V
0V
3.5 V
1.5 V
t
PHZ
V
OH
– 0.3 V
1.5 V
0V
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
SA00012
t
PLZ
NOTES:
1. All input pulses are supplied by generators having the following
characteristics: PRR
≤
10 MHz, Z
O
= 50
Ω,
t
r
≤
2.5 ns, t
f
≤
2.5 ns.
2. The outputs are measured one at a time with one transition per
measurement.
V
OL
+ 0.3 V
V
OL
V
OH
SA00029
Waveform 2. 3-State Output Enable and Disable Times
NOTES:
1. t
PLZ
and t
PHZ
are the same as t
dis
.
2. t
PZL
and t
PZH
are the same as t
en
.
3. t
PLH
and t
PHL
are the same as t
pd
.
2002 Sep 09
5
嵌入式系统
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