Universal Octal T1/E1/J1 LIU with Inte-
grated Clock Adapter
IDT82P5088
FEATURES
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Eight channel T1/E1/J1 long haul/short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024
KHz
Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
3.3 V and 1.8 V power supply with 5 V tolerant inputs
Meets or exceeds specifications in
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ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703,G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR 12/13
- AT&T Pub 62411
Per channel software selectable on:
- Wave-shaping templates for short haul and long haul LBO (Line Build
Out)
- Line terminating impedance (T1:100
Ω,
J1:110
Ω,
E1:75
Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path and transmit path)
- Single rail/dual rail system interfaces
-
B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
Active level of transmit data (TDATA) and receive data (RDATA)
Receiver or transmitter power down
High impedance setting for line drivers
PRBS (Pseudo Random Bit Sequence) generation and detection
with 2
15
-1 PRBS polynomials for E1
- QRSS (Quasi Random Sequence Signals) generation and detection
with 2
20
-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Per channel cable attenuation indication
Adaptive receive sensitivity
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection for line drivers
LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces
Package:
Available in 256-pin PBGA
Green package options available
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DESCRIPTION
The IDT82P5088 is an eight port line intereface that can be configured
per port to any combination of T1, E1 or J1 ports. In receive path, an Adaptive
Equalizer is integrated to remove the distortion introduced by the cable
attenuation. The IDT82P5088 also performs clock/data recovery, AMI/
B8ZS/HDB3 line decoding and detects and reports the LOS conditions. In
transmit path, there is an AMI/B8ZS/HDB3 encoder, Waveform Shaper,
LBOs and Jitter Attenuator for each channel. The Jitter Attenuators in trans-
mit path and receive path both can be disabled. The IDT82P5088 supports
both Single Rail and Dual Rail system interfaces. To facilitate the network
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
each channel, and different types of loopbacks can be set on a per channel
basis. Four different kinds of line terminating impedance, 75Ω, 100
Ω,
110
Ω
and 120
Ω
are selectable on a per channel basis. The chip also provides
driver short-circuit protection and supports JTAG boundary scanning.
The IDT82P5088 can be used in SDH/SONET, LAN, WAN, Routers,
Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay
Access Devices, CSU/DSU equipment, etc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
2009 Integrated Device Technology, Inc.
February 5, 2009
DSC-7216/-
IDT82P5088
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
One of the Eight Identical Channels
LOS/AIS
Detector
RTIPn
RRINGn
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
Clock and
Data
Recovery
Receiver
Internal
Termination
LOSn
RCLKn
RDn/RDPn
CVn/RDNn
PRBS Detector
IBLC Detector
Remote
Loopback
Jitter
Attenuator
Line
Driver
Waveform
Shaper/LBO
Digital
Loopback
Analog
Loopback
TTIPn
Transmitter
Internal
Termination
TRINGn
Figure-1 Block Diagram
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
2
Control Interface
TCLKn
TDn/TDPn
TDNn
B8ZS/
HDB3/AMI
Encoder
PRBS Generator
IBLC Generator
TAOS
Clock Generator
JTAG TAP
VDDDIO / VDDDC /
VDDAR / VDDAT /
VDDAX / VDDAP /
VDDAB
G.772
Monitor
TDO
TDI
TMS
TCK
TRST
GPIO[1:0]
RESET
THZ
A[10:0]
D[7:1]
D[0]/SDO
CS
REFR
RW/WR/SDI
DS/RD/SCLK
MPM
SPIEN
INT
REFB_OUT
REFA_OUT
CLK_SEL[2:0]
OSCO
OSCI
CLK_GEN_1.544
CLK_GEN_2.048
GNDD / GNDA
February 5, 2009
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
Tables of Contents
1
2
3
IDT82P5088 PIN CONFIGURATIONS .......................................................................................... 9
PIN DESCRIPTION ..................................................................................................................... 10
FUNCTIONAL DESCRIPTION .................................................................................................... 17
3.1
T1/E1/J1 MODE SELECTION .......................................................................................... 17
3.2
TRANSMIT PATH ............................................................................................................. 17
3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 17
3.2.2 ENCODER .............................................................................................................. 17
3.2.3 PULSE SHAPER .................................................................................................... 17
3.2.3.1 Preset Pulse Templates .......................................................................... 17
3.2.3.2 LBO (Line Build Out) ............................................................................... 18
3.2.3.3 User-Programmable Arbitrary Waveform ................................................ 18
3.2.4 TRANSMIT PATH LINE INTERFACE..................................................................... 22
3.2.5 TRANSMIT PATH POWER DOWN ........................................................................ 22
3.2.6 TRANSMIT JITTER ATTENUATOR ....................................................................... 22
3.3
RECEIVE PATH ............................................................................................................... 24
3.3.1 RECEIVE INTERNAL TERMINATION.................................................................... 24
3.3.2 LINE MONITOR ...................................................................................................... 25
3.3.3 ADAPTIVE EQUALIZER......................................................................................... 25
3.3.4 RECEIVE SENSITIVITY ......................................................................................... 25
3.3.5 DATA SLICER ........................................................................................................ 25
3.3.6 CDR (Clock & Data Recovery)................................................................................ 25
3.3.7 DECODER .............................................................................................................. 25
3.3.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 25
3.3.9 RECEIVE PATH POWER DOWN........................................................................... 25
3.3.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 26
3.3.11 RECEIVE JITTER ATTENUATOR.......................................................................... 26
3.3.12 LOS AND AIS DETECTION.................................................................................... 27
3.3.12.1 LOS DETECTION.................................................................................... 27
3.3.12.2 AIS DETECTION ..................................................................................... 29
3.4
TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 30
3.4.1 TRANSMIT ALL ONES ........................................................................................... 30
3.4.2 TRANSMIT ALL ZEROS......................................................................................... 30
3.4.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 30
3.5
LOOPBACK ...................................................................................................................... 31
3.5.1 ANALOG LOOPBACK ............................................................................................ 31
3.5.2 DIGITAL LOOPBACK ............................................................................................. 31
3.5.3 REMOTE LOOPBACK............................................................................................ 31
Tables of Contents
3
February 5, 2009
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
4
3.5.4 INBAND LOOPBACK.............................................................................................. 33
3.5.4.1 Transmit Activate/Deactivate Loopback Code......................................... 33
3.5.4.2 Receive Activate/Deactivate Loopback Code.......................................... 33
3.5.4.3 Automatic Remote Loopback .................................................................. 33
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 34
3.6.1 DEFINITION OF LINE CODING ERROR ............................................................... 34
3.6.2 ERROR DETECTION AND COUNTING ................................................................ 34
3.6.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 35
LINE DRIVER FAILURE MONITORING ........................................................................... 35
CLOCK GENERATOR AND TCLK ................................................................................... 36
3.8.1 CLOCK GENERATOR............................................................................................ 36
3.8.2 TRANSMIT CLOCK (TCLK).................................................................................... 36
MICROPROCESSOR INTERFACE ................................................................................. 37
3.9.1 SPI Mode ................................................................................................................ 37
3.9.2 Parallel Microprocessor Interface ........................................................................... 37
INTERRUPT HANDLING .................................................................................................. 38
GENERAL PURPOSE I/O ................................................................................................ 39
RESET OPERATION ........................................................................................................ 39
POWER SUPPLY ............................................................................................................. 39
PROGRAMMING INFORMATION .............................................................................................. 40
4.1
REGISTER LIST AND MAP ............................................................................................. 40
4.2
RESERVED REGISTERS ................................................................................................ 40
4.3
REGISTER DESCRIPTION .............................................................................................. 42
4.3.1 GLOBAL REGISTERS............................................................................................ 42
4.3.2 PER CHANNEL CONTROL REGISTERS .............................................................. 44
4.3.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 44
4.3.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 47
4.3.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 49
4.3.6 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 52
4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 52
4.3.8 LINE STATUS REGISTERS ................................................................................... 55
4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 58
4.3.10 COUNTER REGISTERS ........................................................................................ 59
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 60
5.1
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 61
5.2
JTAG DATA REGISTER ................................................................................................... 61
5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 61
5.2.2 BYPASS REGISTER (BR)...................................................................................... 61
5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 61
5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 62
TEST SPECIFICATIONS ............................................................................................................ 64
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Tables of Contents
4
February 5, 2009
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
Absolute maximum Ratings .............................................................................................. 64
Recommended Operating Conditions ............................................................................... 64
D.C. Characteristics .......................................................................................................... 65
T1/J1 Line Receiver Electrical Characteristics ................................................................. 66
E1 Line Receiver Electrical Characteristics ...................................................................... 67
T1/J1 Line Transmitter Electrical Characteristics ............................................................. 67
E1 Line Transmitter Electrical Characteristics .................................................................. 68
Transmitter and Receiver Timing Characteristics ............................................................. 69
Jitter Tolerance ................................................................................................................. 70
6.9.1 T1/J1 Mode ............................................................................................................. 70
6.9.2 E1 Mode.................................................................................................................. 71
Jitter Transfer .................................................................................................................... 73
6.10.1 T1/J1 Mode ............................................................................................................. 73
6.10.2 E1 Mode.................................................................................................................. 74
7
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 77
7.1
Motorola Non-Multiplexed Mode ....................................................................................... 77
7.1.1 Read Cycle Specification ........................................................................................ 77
7.1.2 Write Cycle Specification ........................................................................................ 77
7.2
Intel Non-Multiplexed Mode .............................................................................................. 78
7.2.1 Read Cycle Specification ........................................................................................ 78
7.2.2 Write Cycle Specification ........................................................................................ 79
7.3
SPI Mode .......................................................................................................................... 80
Tables of Contents
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February 5, 2009
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