82V3011PVG8: 产品描述SSOP-56, Reel; 产品类别电信电路; 文件大小486KB，共32页; 制造商IDT (Integrated Device Technology); 标准

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82V3011PVG8概述

SSOP-56, Reel

82V3011PVG8规格参数

参数名称	属性值
Brand Name	Integrated Device Technology
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	SSOP
包装说明	SSOP,
针数	56
制造商包装代码	PVG56
Reach Compliance Code	compliant
ECCN代码	EAR99
Is Samacsys	N
JESD-30 代码	R-PDSO-G56
JESD-609代码	e3
长度	18.415 mm
湿度敏感等级	1
功能数量	1
端子数量	56
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	SSOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	260
认证状态	Not Qualified
座面最大高度	2.794 mm
标称供电电压	3.3 V
表面贴装	YES
电信集成电路类型	TELECOM CIRCUIT
温度等级	INDUSTRIAL
端子面层	Matte Tin (Sn) - annealed
端子形式	GULL WING
端子节距	0.635 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	7.5 mm
Base Number Matches	1

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T1/E1/OC3 WAN PLL WITH

SINGLE REFERENCE INPUT

FEATURES

• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum

4 Enhanced and Stratum 4 timing for DS1 interfaces

• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing

for E1 interface

• Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44

MHz

• Provides C1.5o,

C3o,

C2o,

C4o,

C6o, C8o,

C16o,

C19o and

C32o

output clock signals

• Provides 7 types of 8 kHz framing pulses:

F0o,

F8o,

F16o,

F19o,

F32o,

RSP and TSP

• Provides a C2/C1.5 output clock signal with the frequency

controlled by the reference input Fref

•

IDT82V3011

Holdover frequency accuracy of 0.025 ppm

Phase slope of 5 ns per 125 µs

Attenuates wander from 2.1 Hz

Fast lock mode

Provides Time Interval Error (TIE) correction

MTIE of 600 ns

JTAG boundary scan

Holdover status indication

Freerun status indication

Normal status indication

Lock status indication

Input reference quality indication

3.3 V operation with 5 V tolerant I/O

Package available: 56-pin SSOP (Green option available)

FUNCTIONAL BLOCK DIAGRAM

TDO

TDI

OSCi

TCLR

RST

DDD

DDA

C2/C1.5

TCK

TMS

TRST

FLOCK

JTAG

OSC

C32o

C19o

C19POS

C19NEG

C16o

C8o

C4o

C2o

TIE Control

Block

Virtual

Reference

DPLL

C3o

C1.5o

C6o

F0o

F8o

MON_out

Reference

Input Monitor

Invalid Input

Signal

Detection

F16o

F19o

F32o

RSP

TSP

LOCK

Fref

Feedback Signal

State Control Circuit

Input Frequency

Selection

TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun

F_sel1 F_sel0

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

2006

Integrated Device Technology, Inc.

May 24, 2006

DSC-6237/5

TABLE OF CONTENTS

Pin Description...................................................................................................................................................................................................7

Functional Description ......................................................................................................................................................................................9

2.1 State Control Circuit ..................................................................................................................................................................................9

2.1.1 Normal Mode..............................................................................................................................................................................10

2.1.2 Fast Lock Mode..........................................................................................................................................................................10

2.1.3 Holdover Mode ...........................................................................................................................................................................10

2.1.4 Freerun Mode.............................................................................................................................................................................10

2.2 Frequency Select Circuit .........................................................................................................................................................................10

2.3 Reference Input Monitor ..........................................................................................................................................................................10

2.4 Invalid Input Signal Detection ..................................................................................................................................................................10

2.5 TIE Control Block.....................................................................................................................................................................................11

2.6 DPLL Block..............................................................................................................................................................................................13

2.6.1 Phase Detector (PHD)................................................................................................................................................................13

2.6.2 Limiter.........................................................................................................................................................................................13

2.6.3 Loop Filter ..................................................................................................................................................................................13

2.6.4 Fraction Block.............................................................................................................................................................................13

2.6.5 Digital Control Oscillator (DCO)..................................................................................................................................................13

2.6.6 Lock Indicator .............................................................................................................................................................................13

2.6.7 Output Interface..........................................................................................................................................................................13

2.7 OSC.........................................................................................................................................................................................................13

2.7.1 Clock Oscillator ..........................................................................................................................................................................13

2.8 JTAG .......................................................................................................................................................................................................14

2.9 Reset Circuit ............................................................................................................................................................................................14

2.10 Power Supply Filtering Techniques .........................................................................................................................................................15

Measures of Performance ...............................................................................................................................................................................16

3.1 Intrinsic Jitter ...........................................................................................................................................................................................16

3.2 Jitter Tolerance........................................................................................................................................................................................16

3.3 Jitter Transfer ..........................................................................................................................................................................................16

3.4 Frequency Accuracy................................................................................................................................................................................16

3.5 Holdover Accuracy ..................................................................................................................................................................................16

3.6 Capture Range ........................................................................................................................................................................................16

3.7 Lock Range .............................................................................................................................................................................................16

3.8 Phase Slope ............................................................................................................................................................................................16

3.9 Time Interval Error (TIE)..........................................................................................................................................................................16

3.10 Maximum Time Interval Error (MTIE) ......................................................................................................................................................16

3.11 Phase Continuity .....................................................................................................................................................................................17

3.12 Phase Lock Time.....................................................................................................................................................................................17

Absolute Maximum Ratings ............................................................................................................................................................................18

Recommended DC Operating Conditions .....................................................................................................................................................18

DC Electrical Characteristics ..........................................................................................................................................................................18

6.1 Single End Input/Output Port...................................................................................................................................................................18

6.2 Differential Output Port (LVDS) ...............................................................................................................................................................19

AC Electrical Characteristics ..........................................................................................................................................................................20

7.1 Performance ............................................................................................................................................................................................20

7.2 Intrinsic Jitter Unfiltered ...........................................................................................................................................................................21

7.3 C1.5o (1.544 MHz) Intrinsic Jitter Filtered ...............................................................................................................................................21

7.4 C2o (2.048 MHz) Intrinsic Jitter Filtered ..................................................................................................................................................21

7.5 C19o (19.44 MHz) Intrinsic Jitter Filtered ................................................................................................................................................21

7.6 8 kHz Input to 8 kHz Output Jitter Transfer .............................................................................................................................................22

7.7 1.544 MHz Input to 1.544 MHz Output Jitter Transfer.............................................................................................................................22

7.8 2.048 MHz Input to 2.048 MHz Output Jitter Transfer.............................................................................................................................22

7.9 19.44 MHz Input to 19.44 MHz Output Jitter Transfer.............................................................................................................................23

May 24, 2006

Table Of Contents

LIST OF FIGURES

Figure - 1

Figure - 2

Figure - 3

Figure - 4

Figure - 5

Figure - 6

Figure - 7

Figure - 8

Figure - 9

Figure - 10

Figure - 11

Figure - 12

Figure - 13

Figure - 14

Figure - 15

IDT82V3011 SSOP56 Package Pin Assignment ................................................................................................................................ 2

State Control Circuit ............................................................................................................................................................................ 9

State Control Diagram......................................................................................................................................................................... 9

TIE Control Block Diagram................................................................................................................................................................ 11

Reference Switch with TIE Control Block Enabled............................................................................................................................ 11

Reference Switch with TIE Control Block Disabled........................................................................................................................... 12

DPLL Block Diagram ......................................................................................................................................................................... 12

Clock Oscillator Circuit ...................................................................................................................................................................... 14

Power-Up Reset Circuit..................................................................................................................................................................... 14

IDT82V3011 Power Decoupling Scheme.......................................................................................................................................... 15

Timing Parameter Measurement Voltage Levels .............................................................................................................................. 26

Input to Output Timing (Normal Mode).............................................................................................................................................. 28

Output Timing 1................................................................................................................................................................................. 29

Output Timing 2................................................................................................................................................................................. 30

Input Control Setup and Hold Timing ................................................................................................................................................ 30

List of Figures

May 24, 2006

82V3011PVG8相似产品对比

	82V3011PVG8	82V3011PVG
描述	SSOP-56, Reel	SSOP-56, Tube
Brand Name	Integrated Device Technology	Integrated Device Technology
是否无铅	不含铅	不含铅
是否Rohs认证	符合	符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	SSOP	SSOP
包装说明	SSOP,	SSOP,
针数	56	56
制造商包装代码	PVG56	PVG56
Reach Compliance Code	compliant	compliant
ECCN代码	EAR99	EAR99
Is Samacsys	N	N
JESD-30 代码	R-PDSO-G56	R-PDSO-G56
JESD-609代码	e3	e3
长度	18.415 mm	18.415 mm
湿度敏感等级	1	1
功能数量	1	1
端子数量	56	56
最高工作温度	85 °C	85 °C
最低工作温度	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SSOP	SSOP
封装形状	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	260	260
认证状态	Not Qualified	Not Qualified
座面最大高度	2.794 mm	2.794 mm
标称供电电压	3.3 V	3.3 V
表面贴装	YES	YES
电信集成电路类型	TELECOM CIRCUIT	TELECOM CIRCUIT
温度等级	INDUSTRIAL	INDUSTRIAL
端子面层	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
端子形式	GULL WING	GULL WING
端子节距	0.635 mm	0.635 mm
端子位置	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30
宽度	7.5 mm	7.5 mm
Base Number Matches	1	1

82V3011PVG8

82V3011PVG8在线购买

82V3011PVG8概述

82V3011PVG8规格参数

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82V3011PVG8相似产品对比

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