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SiI1161CT100: 产品描述SPECIALTY CONSUMER CIRCUIT, PQFP100; 产品类别半导体其他集成电路（IC）; 文件大小389KB，共46页; 制造商SILICONIMAGE; 官网地址http://www.siliconimage.com/

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SiI1161CT100概述

SPECIALTY CONSUMER CIRCUIT, PQFP100

专业消费类电路, PQFP100

SiI1161CT100规格参数

参数名称	属性值
功能数量	1
端子数量	100
最大工作温度	70 Cel
最小工作温度	0.0 Cel
最大供电/工作电压	3.6 V
最小供电/工作电压	3 V
加工封装描述	铅 FREE, MS026-AED-HD, TQFP-100
无铅	Yes
欧盟RoHS规范	Yes
中国RoHS规范	Yes
状态	ACTIVE
工艺	CMOS
包装形状	SQUARE
包装尺寸	FLATPACK, THIN PROFILE, FINE PITCH
表面贴装	Yes
端子形式	GULL WING
端子间距	0.5000 mm
端子涂层	NOT SPECIFIED
端子位置	四
包装材料	塑料/环氧树脂
温度等级	COMMERCIAL
消费IC类型	消费类电路

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Technology

SiI 1161

PanelLink Receiver

Data Sheet

Document #

SiI-DS-0096-D

SiI

1161 PanelLink Receiver

Data Sheet

TABLE OF CONTENTS

SiI

1161 Pin Diagram ....................................................................................................................1

Functional Description .................................................................................................................2

Electrical Specifications...............................................................................................................3

Absolute Maximum Conditions ................................................................................................................... 3

Normal Operating Conditions ..................................................................................................................... 3

Digital I/O Specifications ............................................................................................................................. 3

General DC Specifications .......................................................................................................................... 4

General AC Specifications .......................................................................................................................... 5

Compatibility Mode Selection Specifications.............................................................................6

SiI

161B (Compatible) Mode DC Specifications ......................................................................................... 6

SiI

161B (Compatible) Mode AC Specifications.......................................................................................... 8

SiI

1161 (Programmable) Mode DC Specifications .................................................................................... 9

SiI

1161 (Programmable) Mode AC Specifications................................................................................... 11

Timing Diagrams.........................................................................................................................15

Pin Descriptions..........................................................................................................................19

Output Pins ............................................................................................................................................... 19

Differential Signal Data Pins ..................................................................................................................... 19

Configuration Pins..................................................................................................................................... 20

Power Management Pins.......................................................................................................................... 20

Power and Ground Pins............................................................................................................................ 21

Feature Information ....................................................................................................................22

HSYNC De-jitter Function ......................................................................................................................... 22

Clock Detect Function............................................................................................................................... 22

OCK_INV Function ................................................................................................................................... 22

C Slave Interface .................................................................................................................................... 23

TFT Panel Data Mapping .......................................................................................................................... 24

Design Recommendations.........................................................................................................31

Differences Between

SiI

161B and

SiI

1161............................................................................................. 31

Using

SiI

1161 in Multiple-Input Applications............................................................................................ 32

Using

SiI

1161 to Replace TI TFP401 ...................................................................................................... 32

Adjusting Equalizer and Bandwidth .......................................................................................................... 33

Voltage Ripple Regulation......................................................................................................................... 34

Decoupling Capacitors.............................................................................................................................. 35

Series Damping Resistors on Outputs...................................................................................................... 36

Receiver Layout ........................................................................................................................................ 37

PCB Ground Planes.................................................................................................................................. 38

Staggered Outputs and Two Pixels per Clock .......................................................................................... 38

Adjusting Output Timings for Loading....................................................................................................... 38

Packaging ....................................................................................................................................39

Thermal Design Options ........................................................................................................................... 39

ePad Enhancement .................................................................................................................................. 39

Dimensions and Marking .......................................................................................................................... 41

Ordering Information ..................................................................................................................41

iii

SiI-DS-0096-D

SiI

1161 PanelLink Receiver

Data Sheet

LIST OF TABLES

Table 1. DC Parametric Specifications ........................................................................................................... 4

Table 2. General AC Specifications ................................................................................................................ 5

Table 3.

SiI

161B Mode DC Specifications ..................................................................................................... 7

Table 4.

SiI

161B Mode AC Specifications ..................................................................................................... 8

Table 5.

SiI

1161 Mode DC Specifications.................................................................................................... 10

Table 6.

SiI

1161 Mode AC Specifications .................................................................................................... 11

Table 7. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=0.................................... 13

Table 8. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=1.................................... 14

Table 9. One Pixel per Clock Mode Data Mapping....................................................................................... 24

Table 10. Two Pixel per Clock Mode Data Mapping..................................................................................... 24

Table 11. One Pixel per Clock Input/Output TFT Mode – VESA P&D and FPDI-2

Compliant.................. 25

Table 12. Two Pixels per Clock Input/Output TFT Mode .............................................................................. 26

Table 13. 24-bit One Pixel per Clock Input with 24-bit Two Pixels per Clock Output TFT Mode ................. 27

Table 14. 18-bit One Pixel per Clock Input with 18-bit Two Pixels per Clock Output TFT Mode ................. 28

Table 15. Two Pixels per Clock Input with One Pixel per Clock Output TFT Mode ..................................... 29

Table 16. Output Clock Configuration by Typical TFT Panel Application ..................................................... 30

Table 17. New Pin Functions for

SiI

1161 in Programmable Mode .............................................................. 31

Table 18. Internal I

C Registers.................................................................................................................... 33

Table 19: I

C Register Field Definitions ........................................................................................................ 34

Table 20. Recommended Components for 1-2MHz Noise Suppression...................................................... 36

Table 21. Recommended Components for 100-200kHz Noise Suppression on PVCC .............................. 36

LIST OF FIGURES

Figure 1. Functional Block Diagram ............................................................................................................... 2

Figure 2.

SiI

161B Mode Control of Output Pin Drive Strength ...................................................................... 6

Figure 3. Output Loading in

SiI

161B Mode ................................................................................................... 9

Figure 4.

SiI

1161 Mode Control of Output Pin Drive Strength....................................................................... 9

Figure 5. Receiver Output Setup and Hold Times – OCK_INV=0................................................................ 12

Figure 6. Receiver Output Setup and Hold Times – OCK_INV=1................................................................ 13

Figure 7. Digital Output Transition Times ..................................................................................................... 15

Figure 8. Receiver Clock Cycle/High/Low Times ......................................................................................... 15

Figure 9. Channel-to-Channel Skew Timing ................................................................................................ 15

Figure 10. Receiver Clock-to-Output Delay and Duty Cycle Limits ............................................................. 16

Figure 11. Output Signals Disabled Timing from Clock Inactive .................................................................. 16

Figure 12. Wake-Up on Clock Detect .......................................................................................................... 16

Figure 13. Output Signals Disabled Timing from PD# Active ....................................................................... 17

Figure 14. SCDT Timing from DE Inactive or Active .................................................................................... 17

Figure 15. Two Pixels per Clock Staggered Output Timing Diagram ........................................................... 17

Figure 16. I

C Data Valid Delay (driving Read Cycle data) .......................................................................... 18

Figure 17. I

C Reset Timing at Power-Up or Prior to first I

C Acess............................................................ 18

Figure 18. Block Diagram for OCK_INV....................................................................................................... 22

Figure 19. I

C Byte Read.............................................................................................................................. 23

Figure 20. I

C Byte Write .............................................................................................................................. 23

Figure 21. RESET Generation Delay ........................................................................................................... 31

Figure 22. Recommended RESET Circuit.................................................................................................... 32

Figure 23. Voltage Regulation using TL431 ................................................................................................. 34

Figure 24. Voltage Regulation using LM317 ................................................................................................ 35

Figure 25. Decoupling and Bypass Capacitor Placement............................................................................ 35

Figure 26. Decoupling and Bypass Schematic............................................................................................. 36

Figure 27. Receiver Output Series Damping Resistors ............................................................................... 36

Figure 28. General Signal Routing Recommendations................................................................................ 37

Figure 29. Signal Trace Routing Example.................................................................................................... 37

Figure 30. ePad Diagram ............................................................................................................................. 39

Figure 31. Temperature Rise with Frequency and ePad.............................................................................. 40

Figure 32. Package Diagram........................................................................................................................ 41

SiI-DS-0096-D

SiI1161CT100相似产品对比

	SiI1161CT100	SII1161	SiI1161CTU
描述	SPECIALTY CONSUMER CIRCUIT, PQFP100	SPECIALTY CONSUMER CIRCUIT, PQFP100	SPECIALTY CONSUMER CIRCUIT, PQFP100
功能数量	1	1	1
端子数量	100	100	100
最大工作温度	70 Cel	70 Cel	70 Cel
最小工作温度	0.0 Cel	0.0 Cel	0.0 Cel
最大供电/工作电压	3.6 V	3.6 V	3.6 V
最小供电/工作电压	3 V	3 V	3 V
加工封装描述	铅 FREE, MS026-AED-HD, TQFP-100	铅 FREE, MS026-AED-HD, TQFP-100	铅 FREE, MS026-AED-HD, TQFP-100
无铅	Yes	Yes	Yes
欧盟RoHS规范	Yes	Yes	Yes
中国RoHS规范	Yes	Yes	Yes
状态	ACTIVE	ACTIVE	ACTIVE
工艺	CMOS	CMOS	CMOS
包装形状	SQUARE	SQUARE	SQUARE
包装尺寸	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH
表面贴装	Yes	Yes	Yes
端子形式	GULL WING	GULL WING	GULL WING
端子间距	0.5000 mm	0.5000 mm	0.5000 mm
端子涂层	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
端子位置	四	四	四
包装材料	塑料/环氧树脂	塑料/环氧树脂	塑料/环氧树脂
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL
消费IC类型	消费类电路	消费类电路	消费类电路

SiI1161CT100

SiI1161CT100概述

SiI1161CT100规格参数

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