OCTAL T1/E1 SHORT HAUL
LINE INTERFACE UNIT
FEATURES
IDT82V2048
Fully integrated octal T1/E1 short haul line interface which
supports 100
T1 twisted pair, 120
E1 twisted pair and 75
E1 coaxial applications
Selectable Single Rail mode or Dual Rail mode and AMI or
B8ZS/HDB3 encoder/decoder
Built-in transmit pre-equalization meets G.703 & T1.102
Selectable transmit/receive jitter attenuator meets ETSI CTR12/
13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications
SONET/SDH optimized jitter attenuator meets ITU G.783
mapping jitter specification
Digital/Analog LOS detector meets ITU G.775, ETS 300 233 and
T1.231
ITU G.772 non-intrusive monitoring for in-service testing for
any one of channel 1 to channel 7
Low impedance transmit drivers with high-Z
Selectable hardware and parallel/serial host interface
Local, Remote and Inband Loopback test functions
Hitless Protection Switching (HPS) for 1 to 1 protection without
relays
JTAG boundary scan for board test
3.3 V supply with 5 V tolerant I/O
Low power consumption
Operating temperature range: -40
°C
to +85
°C
Available in 144-pin Thin Quad Flat Pack (TQFP) and 160-pin
Plastic Ball Grid Array (PBGA) packages
Green package options available
FUNCTIONAL BLOCK DIAGRAM
LOS
Detector
RTIPn
RRINGn
Analog
Loopback
TTIPn
TRINGn
Peak
Detector
Line
Driver
Slicer
CLK&Data
Recovery
(DPLL)
Digital
Loopback
Waveform
Shaper
Transmit
All Ones
G.772
Monitor
Clock
Generator
Control Interface
One of Eight Identical Channels
LOSn
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Remote
Loopback
Jitter
Attenuator
B8ZS/
HDB3/AMI
Encoder
IBLC
Generator
IBLC
Detector
AIS
Detector
TCLKn
TDn/TDPn
BPVIn/TDNn
RCLKn
RDn/RDPn
CVn/RDNn
Register
File
JTAG TAP
VDDIO
VDDT
VDDD
VDDA
OE
CLKE
MODE[2:0]
CS/JAS
TS2/SCLK/ALE/AS
TS1/RD/R/W
TS0/SDI/WR/DS
SDO/RDY/ACK
INT
LP[7:0]/D[7:0]/AD[7:0]
MC[3:0]/A[4:0]
MCLK
Figure-1 Block Diagram
TRST
TCK
TMS
TDI
TDO
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
November 14, 2012
1
DSC-6037/19
2010- Integrated Device Technology, Inc.
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
DESCRIPTION
The IDT82V2048 is a single chip, 8-channel T1/E1 short haul PCM
transceiver with a reference clock of 1.544 MHz (T1) or 2.048 MHz (E1).
The IDT82V2048 contains 8 transmitters and 8 receivers.
All the receivers and transmitters can be programmed to work either
in Single Rail mode or Dual Rail mode. B8ZS/HDB3 or AMI encoder/
decoder is selectable in Single Rail mode. Pre-encoded transmit data in
NRZ format can be accepted when the device is configured in Dual Rail
mode. The receivers perform clock and data recovery by using inte-
grated digital phase-locked loop. As an option, the raw sliced data (no
retiming) can be output on the receive data pins. Transmit equalization is
implemented with low-impedance output drivers that provide shaped
waveforms to the transformer, guaranteeing template conformance.
A jitter attenuator is integrated in the IDT82V2048 and can be
switched into either the transmit path or the receive path for all channels.
The jitter attenuation performance meets ETSI CTR12/13, ITU G.736,
G.742, G.823, and AT&T Pub 62411 specifications.
The IDT82V2048 offers hardware control mode and software control
mode. Software control mode works with either serial host interface or
parallel host interface. The latter works via an Intel/Motorola compatible
8-bit parallel interface for both multiplexed or non-multiplexed applica-
tions. Hardware control mode uses multiplexed pins to select different
operation modes when the host interface is not available to the device.
The IDT82V2048 also provides loopback and JTAG boundary scan
testing functions. Using the integrated monitoring function, the
IDT82V2048 can be configured as a 7-channel transceiver with non-
intrusive protected monitoring points.
The IDT82V2048 can be used for SDH/SONET multiplexers, central
office or PBX, digital access cross connects, digital radio base stations,
remote wireless modules and microwave transmission systems.
PIN CONFIGURATIONS
TD4/TDP4
TCLK4
LOS5
CV5/RDN5
RD5/RDP5
RCLK5
BPVI5/TDN5
TD5/TDP5
TCLK5
TDI
TDO
TCK
TMS
TRST
IC
IC
VDDIO
GNDIO
VDDA
GNDA
MODE0/CODE
CS/JAS
TS2/SCLK/ALE/AS
TS1/RD/R/W
TS0/SDI/WR/DS
SDO/RDY/ACK
INT
TCLK2
TD2/TDP2
BPVI2/TDN2
RCLK2
RD2/RDP2
CV2/RDN2
LOS2
TCLK3
TD3/TDP3
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TD7/TDP7
TCLK7
LOS6
CV6/RDN6
RD6/RDP6
RCLK6
BPVI6/TDN6
TD6/TDP6
TCLK6
MCLK
MODE2
A4
MC3/A3
MC2/A2
MC1/A1
MC0/A0
VDDIO
GNDIO
VDDD
GNDD
LP0/D0/AD0
LP1/D1/AD1
LP2/D2/AD2
LP3/D3/AD3
LP4/D4/AD4
LP5/D5/AD5
LP6/D6/AD6
LP7/D7/AD7
TCLK1
TD1/TDP1
BPVI1/TDN1
RCLK1
RD1/RDP1
CV1/RDN1
LOS1
TCLK0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
BPVI4/TDN4
RCLK4
RD4/RDP4
CV4/RDN4
LOS4
OE
CLKE
VDDT4
TTIP4
TRING4
GNDT4
RTIP4
RRING4
GNDT5
TRING5
TTIP5
VDDT5
RRING5
RTIP5
VDDT6
TTIP6
TRING6
GNDT6
RTIP6
RRING6
GNDT7
TRING7
TTIP7
VDDT7
RRING7
RTIP7
LOS7
CV7/RDN7
RD7/RDP7
RCLK7
BPVI7/TDN7
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
IDT82V2048
(Top View)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
BPVI3/TDN3
RCLK3
RD3/RDP3
CV3/RDN3
LOS3
RTIP3
RRING3
VDDT3
TTIP3
TRING3
GNDT3
RRING2
RTIP2
GNDT2
TRING2
TTIP2
VDDT2
RTIP1
RRING1
VDDT1
TTIP1
TRING1
GNDT1
RRING0
RTIP0
GNDT0
TRING0
TTIP0
VDDT0
MODE1
LOS0
CV0/RDN0
RD0/RDP0
RCLK0
BPVI0/TDN0
TD0/TDP0
Figure-2 TQFP144 Package Pin Assignment
2
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RCLK
7
RDP
7
RDN
7
VDDT
7
TRING
7
B
TCLK
7
TDP
7
TDN
7
VDDT
7
TTIP
7
C
RCLK
6
RDP
6
RDN
6
VDDT
6
TRING
6
D
E
F
MC
1
MC
2
MC
3
A4
G
H
J
LP
6
LP
5
LP
4
LP
3
K
LP
7
MODE
1
LOS
1
LOS
0
L
TCLK
1
TDP
1
TDN
1
VDDT
1
TTIP
1
M
RCLK
1
RDP
1
RDN
1
VDDT
1
TRING
1
N
TCLK
0
TDP
0
TDN
0
VDDT
0
TTIP
0
P
RCLK
0
RDP
0
RDN
0
VDDT
0
TRING
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TCLK
MCLK
6
TDP
6
TDN
6
VDDT
6
TTIP
6
MODE
2
LOS
6
LOS
7
VDDIO VDDD
LP
0
MC
0
LP
2
LP
1
GNDIO GNDD
GNDT GNDT GNDT GNDT
7
7
6
6
RTIP
7
RTIP
4
RRING
7
RRING
4
RTIP
6
RTIP
5
RRING
6
RRING
5
GNDT GNDT GNDT GNDT
1
1
0
0
IDT82V2048
(Bottom View)
RRING
1
RRING
2
RTIP
1
RTIP
2
RRING
0
RRING
3
RTIP
0
RTIP
3
GNDT GNDT GNDT GNDT
4
4
5
5
TRING
4
VDDT
4
RDN
4
RDP
4
RCLK
4
A
TTIP
4
VDDT
4
TDN
4
TDP
4
TCLK
4
B
TRING
5
VDDT
5
RDN
5
RDP
5
RCLK
5
C
TTIP
5
VDDT
5
TDN
5
TDP
5
TCLK
5
D
LOS
4
LOS
5
CLKE
OE
E
TMS
TDI
TDO
TCK
F
GNDIO GNDA
TRST
IC
MODE
0
IC
CS
TS
2
TS
1
TS
0
J
LOS
3
LOS
2
INT
SDO
K
GNDT GNDT GNDT GNDT
2
2
3
3
TTIP
2
VDDT
2
TDN
2
TDP
2
TCLK
2
L
TRING
2
VDDT
2
RDN
2
RDP
2
RCLK
2
M
TTIP
3
VDDT
3
TDN
3
TDP
3
TCLK
3
N
TRING
3
VDDT
3
RDN
3
RDP
3
RCLK
3
P
VDDIO VDDA
G
H
Figure-3 PBGA160 Package Pin Assignment
3
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
1
PIN DESCRIPTION
Table-1 Pin Description
Name
Type
Pin No.
TQFP144
PBGA160
Transmit and Receive Line Interface
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
45
52
57
64
117
124
129
136
46
51
58
63
118
123
130
135
48
55
60
67
120
127
132
139
49
54
61
66
121
126
133
138
N5
L5
L10
N10
B10
D10
D5
B5
P5
M5
M10
P10
A10
C10
C5
A5
P7
M7
M8
P8
A8
C8
C7
A7
N7
L7
L8
N8
B8
D8
D7
B7
Description
Analog
Output
TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~7
These pins are the differential line driver outputs. They will be in high-Z if pin OE is low or the correspond-
ing pin TCLKn is low (pin OE is global control, while pin TCLKn is per-channel control). In host mode, each
pin can be in high-Z by programming a ‘1’ to the corresponding bit in register
OE
(1)
.
Analog
Input
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~7
These pins are the differential line receiver inputs.
1
. Register name is indicated by bold capital letter. For example,
OE
indicates Output Enable Register.
4
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
Type
Pin No.
TQFP144
PBGA160
Description
Transmit and Receive Digital Data Interface
TDn: Transmit Data for Channel 0~7
When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn is
sampled into the device on the falling edges of TCLKn, and encoded by AMI or B8ZS/HDB3 line code
rules before being transmitted to the line.
BPVIn: Bipolar Violation Insertion for Channel 0~7
Bipolar violation insertion is available in Single Rail mode 2 (see
Table-2 on page 13 and Table-3 on page
14)
with AMI enabled. A low-to-high transition on this pin will make the next logic one to be transmitted on
TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing.
TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input
on this pin. Data on TDPn/TDNn are sampled on the falling edges of TCLKn. The line code in dual rail
mode is as the follow:
TDPn
0
0
1
1
TDNn
0
1
0
1
Output Pulse
Space
Negative Pulse
Positive Pulse
Space
TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
I
BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
BPVI4/TDN4
BPVI5/TDN5
BPVI6/TDN6
BPVI7/TDN7
37
30
80
73
108
101
8
1
38
31
79
72
109
102
7
144
N2
L2
L13
N13
B13
D13
D2
B2
N3
L3
L12
N12
B12
D12
D3
B3
Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding
channel into Single Rail mode 1 (see
Table-2 on page 13
and
Table-3 on page 14).
TCLKn: Transmit Clock for Channel 0~7
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDn/TDPn or TDNn is sampled into the device on the falling edges of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All
Ones (TAOS) state (when MCLK is clocked). In TAOS state, the TAOS generator adopts MCLK as the
clock reference.
If TCLKn is low, the corresponding transmit channel is set into power down state, while driver output ports
become high-Z.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the fol-
lows:
MCLK
Clocked
Clocked
Clocked
Normal operation
Transmit All Ones (TAOS) signals to the line side in the corresponding
High ( 16 MCLK)
transmit channel.
Low ( 64 MCLK) The corresponding transmit channel is set into power down state.
TCLKn is clocked Normal operation
Transmit All Ones (TAOS) signals to the line side
TCLKn is high
in the corresponding transmit channel.
( 16 TCLK1)
Corresponding transmit channel is set into power
TCLKn is low
TCLK1 is clocked
down state.
( 64 TCLK1)
The receive path is not affected by the status of TCLK1. When MCLK
is high, all receive paths just slice the incoming data stream. When
MCLK is low, all the receive paths are powered down.
TCLK1 is unavail-
All eight transmitters (TTIPn & TRINGn) will be in high-Z.
able.
TCLKn
Clocked
Transmit Mode
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
I
36
29
81
74
107
100
9
2
N1
L1
L14
N14
B14
D14
D1
B1
High/Low
High/Low
5
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