电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

74AUP1G07GW

产品描述Low-power buffer with open-drain output
文件大小69KB,共16页
制造商Philips Semiconductors (NXP Semiconductors N.V.)
官网地址https://www.nxp.com/
下载文档 选型对比 全文预览

74AUP1G07GW概述

Low-power buffer with open-drain output

文档预览

下载PDF文档
74AUP1G07
Low-power buffer with open-drain output
Rev. 02 — 14 June 2007
Product data sheet
1. General description
The 74AUP1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G07 provides the single non-inverting buffer with open-drain output. The
output of the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
2. Features
s
Wide supply voltage range from 0.8 V to 3.6 V
s
High noise immunity
s
Complies with JEDEC standards:
x
JESD8-12 (0.8 V to 1.3 V)
x
JESD8-11 (0.9 V to 1.65 V)
x
JESD8-7 (1.2 V to 1.95 V)
x
JESD8-5 (1.8 V to 2.7 V)
x
JESD8-B (2.7 V to 3.6 V)
s
ESD protection:
x
HBM JESD22-A114E Class 3A exceeds 5000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101C exceeds 1000 V
s
Low static power consumption; I
CC
= 0.9
µA
(maximum)
s
Latch-up performance exceeds 100 mA per JESD 78 Class II
s
Inputs accept voltages up to 3.6 V
s
Low noise overshoot and undershoot < 10 % of V
CC
s
I
OFF
circuitry provides partial Power-down mode operation
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C

74AUP1G07GW相似产品对比

74AUP1G07GW 74AUP1G07 74AUP1G07GF 74AUP1G07GM
描述 Low-power buffer with open-drain output Low-power buffer with open-drain output Low-power buffer with open-drain output Low-power buffer with open-drain output
j-flash连接不上LPC4357问题
最近使用LPC4357芯片,用了很久都没有问题,今天突然用KEIL找不到目标板了,JTAG Device Chain中显示为空,同时我用J-flash软件也提示AUTO detection of CPU clock frequency is not supported ......
leixu2 NXP MCU
UPS系统监控软件与网络化管理技术
UPS系统监控软件与网络化管理技术...
zbz0529 工业自动化与控制
【2022得捷电子创新设计大赛】ESP32S2 WIF连网
esp32的wifi连网是最基本功能之一。原来是用idf来配置编译的,今天偿试用vscode ESP-IDF来编译下载工程: 1、打开原来已经安装好的ESP-IDF Explorer。打开示例所在的文件夹: 622772 2、 ......
lugl4313820 DigiKey得捷技术专区
【已解决】请教一个简单的问题,关于烧录
本帖最后由 眼大5子 于 2015-1-27 21:54 编辑 刚刚收到论坛买的STM32F429开发板,但是用STM32 ST-LINK Utility烧录BIN文件提示如下错误187058 同样用这个软件给NUCELO STM32F091烧录同一 ......
眼大5子 stm32/stm8
Polar SI9000_V7_1
Polar SI9000_V7_1 本帖最后由 dreamerjun 于 2009-12-31 22:45 编辑 ]...
dreamerjun PCB设计
FR5739晶振电容配置问题!
FR5739并不像g2553可以内部配置电容,所以在接外部晶振时要外接电容才可以起振: (a) For XT1DRIVE = {0}, C L,ef f ≤ 6 pF. (b) For XT1DRIVE = {1}, 6 pF ≤ C L,ef f ≤ 9 pF. ( ......
wow1919 TI技术论坛

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 799  340  916  341  1048  17  7  19  22  46 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved