SM9503A
Radio Controlled Clock Receiver IC
OVERVIEW
The SM9503A is a BiCMOS IC RCC
*1
receiver IC. It accepts low frequency standard wave input received
from an external antenna, amplifies it, detects the data signal, and outputs a digital time code signal.
Radio controlled clock
FEATURES
I
I
I
I
PINOUT
(Top view)
lim
ina
NC
1
I
I
I
I
I
I
Operating supply voltage range: 1.2 to 3.6V
Operating current consumption: 36µA (typ) @1.5V
Standby current consumption: 0.1µA (max) @1.5V
High sensitivity: 0.3µVrms (typ) input @60kHz
input
Low frequency standard wave range: 35kHz to
80kHz
AGC gain hold function
External crystal filter connection
Some versions by a compensation capacitor to
cancel the crystal parallel capacitor
BiCMOS process
Package:16-pin VSOP, Chip form
ORDERING INFORMATION
Device
Package
SM9503AV
CF9503A
16-pin VSOP
Chip form
PACKAGE DIMENSIONS
(Unit: mm)
4.4 ± 0.2
6.4 ± 0.2
pre
0.275TYP
5.1 ± 0.2
1.15 ± 0.1
0 to 10 °
0.10
+ 0.1
0.22
−
0.05
0.12 M
NIPPON PRECISION CIRCUITS INC.—1
0.10 ± 0.05
0.65
0.5 ± 0.2
ry
16
*1
:
IN2
VDD
PON
OUT
VSS
HLDN
CP
CB
IN1
NC
VSSA
XO1
XO2
XI
LF
8
9
+0
0.15
−
.1
0.05
SM9503A
PAD LAYOUT (CF9503A)
(Unit:
µm)
IN2
(1430,2360)
IN1
NC
VSSA
XO1
XO2
XI
(0,0)
PAD NAME and DIMENSIONS (CF9503A)
Pad number
1
2
3
4
5
6
7
8
9
Pad name
XI
lim
LF
CB
CP
HLDN
VSS
OUT
PON
VDD
VDDA
IN2
NC
IN1
NC
VSSA
XO1
XO2
10
11
12
13
14
15
16
17
pre
ina
ry
13
14
15
9
8
7
6
VDD
PON
OUT
VSS
DA9503
NPC
NC
12
11
10
VDDA
16
17
1
5
4
3
HLDN
CP
CB
2
LF
Chip size: 1.43
×
2.36mm
Chip thickness: 300 ± 30µm
PAD size: 100µm
×
100µm
Chip base: V
SS
Pad dimensions [µm]
X
170
447.5
1230
1230
1230
1230
1230
1230
1230
1259.4
908.4
170
170
170
170
170
170
Y
280.6
220
274.2
543.2
823.4
1042
1266.2
1535.2
1759.4
2110
2110
2055.8
1786.8
1506.6
1276
829.8
560.8
NIPPON PRECISION CIRCUITS INC.—2
SM9503A
BLOCK DIAGRAM
PON
OUT
VSS
HLDN CP
CB
LF
VDD
VDDA
Bias
AGC Control
IN1
AGC Amp
IN2
VSSA
XO1
PIN DESCRIPTION
Pad
number
1
2
3
4
5
6
Pin number
7
8
9
lim
Name
XI
I/O
1
I
A/D
2
A
LF
O
O
A
A
CB
CP
O
A
HLDN
VSS
Ipu
−
D
A
OUT
O
D
D
A
A
A
×
A
×
A
A
A
PON
VDD
Ipu
−
−
I
VDDA
IN2
NC
1
×
I
2
3
IN1
NC
×
4
VSSA
XO1
XO2
−
5
6
O
O
10
11
12
pre
7
8
9
13
14
15
−
10
11
12
16
13
14
15
16
17
1. I: input, O: output, Ipu: input with pull-up resistor, –: supply pin
2. A: analog signal, D: digital signal
ina
ry
Decoder
Peak/Bottom
Hold Det.
LPF
C
C
Post Amp
Rectifier
XO2
XI
Description
Crystal filter input connection
Rectifier LPF capacitor connection
Bottom-hold detector capacitor connection
Peak-hold detector capacitor connection
AGC gain hold control (active LOW)
(
−
) Negative supply input (substrate potential)
Time code output (active LOW)
Standby-mode control input (active LOW)
(+) Positive supply input
(+) Positive supply input (AGC amplifier)
Antenna input 2
No connection (must be open)
Antenna input 1
No connection (must be open)
(−) Negative supply input (AGC amplifier)
Crystal filter output 1
Crystal filter output 2
NIPPON PRECISION CIRCUITS INC.—3
SM9503A
SPECIFICATIONS
Absolute Maximum Ratings
V
SS
= 0V
Parameter
Supply voltage range
Input voltage range
Power dissipation
Storage temperature range
Symbol
V
DD
V
IN
P
D
T
stg
Condition
Rating
−0.3
to 7.0
−0.3
to V
DD
+ 0.3
150
Unit
V
V
16-pin VSOP
16-pin VSOP
Chip form
Recommended Operating Conditions
V
SS
= 0V
Parameter
Supply voltage range
Operating temperature range
Symbol
V
DD
T
opr
pre
NIPPON PRECISION CIRCUITS INC.—4
lim
ina
ry
−55
to 125
−65
to 150
Condition
Rating
1.2 to 3.6
−20
to 70
mW
°C
°C
Unit
V
°C
SM9503A
Electrical Characteristics
V
DD
= 1.2 to 3.6V, V
SS
= 0V, Ta =
−20
to 70°C unless otherwise noted.
Rating
Parameter
Operating supply voltage
Maximum operating current
consumption
1
Normal operating current
consumption
1
Standby mode current consumption
Minimum input voltage range
Maximum input voltage range
Input frequency
Startup time
2
Startup time (PON)
2
Input voltage
Symbol
V
DD
I
DDM
V
DD
= 1.5V, Ta = 25°C, no input signal,
PON: V
SS
, OUT: Open
Condition
min
1.2
–
typ
–
50
max
3.6
80
V
µA
Unit
I
DDT
V
DD
= 1.5V, Ta = 25°C,
0.1mVrms input amplitude (differential
input),
500ms pulsewidth, PON: V
SS
, OUT: Open
PON, HLDN: V
DD
or Open
ina
ry
–
36
–
–
–
0.1
–
0.3
–
1.0
–
80
35
–
–
80
8
–
–
–
8
–
–
0.2
–
V
DD
– 0.2
−1
–
–
–
–
–
1
–
–
0.2
–
–
160
200
300
650
TBD
TBD
9
V
DD
– 0.2
1
–
–
100
400
TBD
TBD
–
–
–
–
–
200
500
800
900
–
f [kHz]
60
L
1
[kH]
TBD
C
1
[fF]
TBD
R
1
[kΩ]
TBD
C
0
[pF]
TBD
µA
I
ST
V
FMIN
V
FMAX
F
IN
t
ON
t
PON
V
IL
V
IH
µA
IN1−IN2 differential input, F
IN
= 60kHz
µVrms
IN1−IN2 differential input, F
IN
= 60kHz
IN1−IN2 differential input
When supply is applied
From standby mode
PON, HLDN
mVrms
kHz
sec
sec
V
V
µA
µA
V
V
sec
ms
ms
ms
ms
ms
ms
dB
PON, HLDN
Input current
I
IL
I
IH
V
IN
= 0V, PON, HLDN
V
IN
= V
DD
, PON, HLDN
I
OL
= 5µA, OUT
Gain hold time
Fall time output propagation delay
3
Rise time output propagation delay
3
LOW-level output pulsewidth
4
(200ms)
LOW-level output pulsewidth
4
(500ms)
LOW-level output pulsewidth
4
(800ms)
LOW-level output pulsewidth
4
(900ms)
Noise rejection ratio
5
pre
S/N
L
1
C
1
R
1
C
0
1. Measured using the standard circuit.
2. The time taken under stable wave input conditions from when power is applied or standby is released, using PON, until stable digital output occurs
within ratings.
3. The time taken, with 10:1 input signal amplitude ratio and 500ms pulsewidth, from when a change in signal input occurs until the output OUT
changes. Note that this characteristic is very dependent on the antenna and crystal filter characteristics. The standard crystal used here has the fol-
lowing equivalent circuit coefficients.
4. Values obtained when using the NPC standard crystal employed here. Note that these values are dependent on the crystal characteristics, and
should be considered as reference values.
5. Time averaged rms values, where the noise is white noise and the measurement bandwidth is determined by the crystal filter equivalent used in the
standard circuit.
lim
V
OH
I
OH
=
−
5µA, OUT
≤ ±
3dB variation
t
HLD
t
DN
t
UP
T
200
T
500
T
800
T
900
Output voltage
V
OL
FIN = 60kHz, NPC standard crystal,
NPC standard jig
NIPPON PRECISION CIRCUITS INC.—5
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