74LVQ299
8 BIT PIPO SHIFT REGISTER
WITH ASYNCHRONOUS CLEAR
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 8.3 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.5V (TYP.) at V
CC
= 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 299
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ299MTR
74LVQ299TTR
DESCRIPTION
The 74LVQ299 is a low voltage CMOS 8 BIT
PIPO SHIFT REGISTER (3-STATE) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power and low noise 3.3V applications.
Figure 1: Pin Connection And IEC Logic Symbols
These devices have four modes (HOLD, SHIFT
LEFT, SHIFT RIGHT and LOAD DATA). Each
mode is chosen by two function select inputs (S0,
S1) as shown in the Truth Table.
When one or both enable inputs, (G1, G2) are
high, the eight input/output terminals are in the
high impedance state; however sequential
operation or clearing of the register is not affected.
Clear function is asynchronous to clock.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2004
Rev. 2
1/15
74LVQ299
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
1, 19
2, 3
7, 13, 6, 14, 5, 15, 4, 16
8, 17
9
11
12
18
10
20
SYMBOL
S0, S1
G1, G2
A/QA to H/QH
QA’,QH’
CLEAR
SR
CLOCK
SL
GND
V
CC
NAME AND FUNCTION
Mode Select Inputs
3-State Output Enable Inputs (Active LOW)
Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver)
Serial Outputs (Standard Output)
Asynchronous Master Reset Input (Active LOW)
Serial Data Shift Right Input
Clock Input (LOW to HIGH, Edge-triggered)
Serial Data Shift Left Input
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
INPUTS
MODE
CLEAR
Z
CLEAR
HOLD
SHIFT
RIGHT
SHIFT
LEFT
LOAD
L
L
L
H
H
H
H
H
H
FUNCTION
SELECTED
S1
H
L
X
L
L
L
H
H
H
S0
H
X
L
L
H
H
L
L
H
OUTPUT
CONTROL
G1*
X
L
L
L
L
L
L
L
X
G2*
X
L
L
L
L
L
L
L
X
X
X
X
X
INPUTS/OUTPUTS
SERIAL
CLOCK
SL
X
X
X
X
X
X
H
L
X
SR
X
X
X
X
H
L
X
X
X
Z
L
L
QA0
H
L
QBn
QBn
a
Z
L
L
QH0
QGn
QGn
H
L
h
L
L
L
QA0
H
L
QBn
QBn
a
L
L
L
QH0
QGn
QGn
H
L
h
A/QA
H/QH
QA’
QH’
OUTPUTS
* When one or both controls are high, the eight input/output terminals are the high impedance state: however sequential operation or cleaning
of the register is not affected.
Z: High Impedance
Qn0: The level of An before the indicated steady state input conditions were established.
Qnn: The level of Qn before the most recent active transition indicated by OR
a, h: The level of the steady state inputs A, H, respectively.
X: Don’t Care
2/15
74LVQ299
Figure 3: Logic Diagram
3/15
74LVQ299
Figure 4: Timing Chart
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
400
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0V (note 2)
Parameter
Value
2 to 3.6
0 to V
CC
0 to V
CC
-55 to 125
0 to 10
Unit
V
V
V
°C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
4/15
74LVQ299
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
T
A
= 25°C
Min.
2.0
0.8
I
O
=-50
µA
3.0
I
O
=-12 mA
I
O
=-24 mA
V
OL
Low Level Output
Voltage
I
O
=50
µA
3.0
I
O
=12 mA
I
O
=24 mA
I
I
I
OZ
Input Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
3.6
3.6
3.6
3.6
V
I
= V
CC
or GND
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
V
I
= V
CC
or GND
V
OLD
= 0.8 V max
V
OHD
= 2 V min
±
0.1
±0.25
4
36
-25
0.002
0
0.1
0.36
2.9
2.58
2.99
2.9
2.48
2.2
0.1
0.44
0.55
±
1
±
2.5
40
25
-25
Typ.
Max.
Value
-40 to 85°C
Min.
2.0
0.8
2.9
2.48
2.2
0.1
0.44
0.55
±
1
±
5.0
40
µA
µA
µA
mA
mA
V
V
Max.
-55 to 125°C
Min.
2.0
0.8
Max.
V
V
Unit
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
3.0 to
3.6
I
CC
I
OLD
I
OHD
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
C
L
= 50 pF
3.3
0.8
V
T
A
= 25°C
Min.
Typ.
0.5
-0.8
2
-0.6
Max.
0.8
V
V
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
Unit
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
5/15
嵌入式系统
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