CYRF8935
WirelessUSB™ NL 2.4 GHz
Low Power Radio
WirelessUSB™ NL 2.4 GHz Low Power Radio
Features
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Fully integrated 2.4 GHz radio on a chip
1 Mbps over-the-air data rate
Transmit power typical: 0 dBm
Receive sensitivity typical: –87 dBm
1 µA typical
[1]
current consumption in sleep state
Closed-loop frequency synthesis
Supports frequency-hopping spread spectrum
On-chip packet framer with 64-byte first in first out (FIFO) data
buffer
Built-in auto-retry-acknowledge protocol simplifies usage
Built-in cyclic redundancy check (CRC), forward error
correction (FEC), data whitening
Supports DC ~ 12 MHz SPI bus interface
Additional outputs for interrupt request (IRQ) generation
Digital readout of received signal strength indication (RSSI)
4 × 4 mm quad flat no-leads (QFN) package, bare die, or wafer
sales
Among the advantages of WirelessUSB-NL are its fast lock times
and channel switching, along with the ability to transmit larger
payloads. Use of longer payload packets, compared to multiple
short payload packets, can reduce overhead, improve overall
power efficiency, and help alleviate spectrum crowding.
Combined with Cypress's enCoRe™ family of USB and wireless
microcontrollers, WirelessUSB-NL also provides the lowest bill
of materials (BOM) cost solution for PC peripheral applications
such as wireless keyboards and mice, as well as best-in-class
wireless performance in other demanding applications such as
toys, remote controls, fitness, automation, presenter tools, and
gaming.
Applications
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Wireless keyboards and mice
Handheld remote controls
Wireless game controllers
Hobby craft control links
Home automation
Industrial wireless links and networks
Cordless audio and low-rate video
Functional Description
WirelessUSB™-NL, optimized to operate in the 2.4-GHz ISM
band, is Cypress's third generation of 2.4-GHz low-power RF
technology, bringing the next level of low-power performance
into a small 4-mm × 4-mm footprint. WirelessUSB-NL
implements a Gaussian frequency-shift keying (GFSK) radio
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
IN
= 3 VDC, Ta = +25 °C.
Cypress Semiconductor Corporation
Document Number: 001-61351 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 19, 2017
Not recommended for new designs
using a differentiated single-mixer, closed-loop modulation
design that optimizes power efficiency and interference
immunity. Closed-loop modulation effectively eliminates the
problem of frequency drift, enabling WirelessUSB-NL to transmit
up to 255-byte payloads without repeatedly having to pay power
penalties for re-locking the phase locked loop (PLL) as in
open-loop designs.
CYRF8935
Logic Block Diagram
V
IN
V
DD_IO
V
OUT
V
DD1
...V
DD7
LDO Linear
Regulator
PKT
FIFO
GFSK
Modulator
PA
Framer
SPI_SS
CLK
MISO
MOSI
RST_n
Synthesizer
VCO
ANT
ANTb
Pwr/ Reset
BRCLK
[2]
Xtal Osc
GFSK
Demodulator
X
Image
Rej. Mxr.
LNA + BPF
XTALi
XTALo
GND GND
Note
2. BRCLK signal is available on bare die only, not packaged parts.
Document Number: 001-61351 Rev. *K
Page 2 of 40
Not recommended for new designs
SPI Registers
CYRF8935
Contents
Pin Configuration ............................................................. 4
Pin Descriptions ............................................................... 4
Functional Overview ........................................................ 5
Power-on and Register Initialization Sequence ........... 5
Enter Sleep and Wakeup ............................................ 6
Packet Data Structure ................................................. 6
FIFO Pointers .............................................................. 6
Packet Payload Length ............................................... 6
Framer: Packet Length Handling ................................. 7
MCU or Application Handles Packet Length ............... 9
Typical Application ......................................................... 12
Setting the Radio Frequency ..................................... 13
Crystal Oscillator ....................................................... 13
Minimum Pin Count ................................................... 14
Reset Pull-up ............................................................. 14
Transmit Power Control ............................................. 14
Reading RSSI ............................................................ 14
Automatic ACK .......................................................... 15
Receive CRC and FEC Result .................................. 15
Sync Word Selection ................................................. 15
Scramble On/Off Selection ........................................ 16
Measuring Receiver Sensitivity ................................. 16
Receive Spurious Responses ................................... 17
RF VCO Calibration ................................................... 17
Regulatory Compliance ................................................. 18
United States FCC .................................................... 18
Register Settings for Test Purposes .......................... 19
Recommendations for PCB Layout .............................. 19
Antenna Type and Location .......................................... 19
IR Reflow Standard ......................................................... 20
Register Definitions ........................................................ 21
Recommended Register Values ................................ 26
Absolute Maximum Ratings .......................................... 28
Operating Range ............................................................. 28
Electrical Characteristics ............................................... 28
SPI .................................................................................... 31
SPI Transaction Formats and Timing ........................ 31
Specifications ............................................................ 32
Electrical Operating Characteristics ............................. 33
State Diagram ................................................................. 34
Ordering Information ...................................................... 35
Ordering Code Definitions ......................................... 35
Package Diagram ............................................................ 36
Acronyms ........................................................................ 37
Document Conventions ................................................. 37
Units of Measure ....................................................... 37
Document History Page ................................................. 38
Sales, Solutions, and Legal Information ...................... 40
Worldwide Sales and Design Support ....................... 40
Products .................................................................... 40
PSoC® Solutions ...................................................... 40
Cypress Developer Community ................................. 40
Technical Support ..................................................... 40
Document Number: 001-61351 Rev. *K
Page 3 of 40
Not recommended for new designs
CYRF8935
Pin Configuration
Figure 1. 24-pin QFN pinout (Top View)
24
23
22
21
20
19
V
DD6
XTALi
XTALo
V
OUT
1
2
V
DD7
V
IN
V
DD1
RST_n
18
V
DD2
MISO
17
3
ANTb
25 GND
MOSI
16
4
5
ANT
CLK
15
V
DD3
PKT
14
13
6
Test2
V
DD_IO
Test3
FIFO
V
DD4
V
DD5
GND
SPI_SS
Pin Descriptions
Table 1. CYRF8935 24-pin QFN (4 × 4 mm) pinout
Pin Number
6, 7
1, 2, 5, 8, 9, 19, 22
3, 4
10
12, 25
11
13
14
15
16
17
18
20
21
23
24
Pin Name
Test2, Test3
V
DD1
to V
DD7
ANTb, ANT
FIFO
GND
V
DD_IO
SPI_SS
PKT
CLK
MOSI
MISO
RST_n
V
IN
V
OUT
XTALo
XTALi
Type
--
PWR
RF
O
GND
PWR
I
O
I
I
O/High-Z
I
PWR
PWR
AO
AI
Description
Reserved for factory test. Do not connect.
Core power supply voltage. Connect all V
DD
pins to V
OUT
pin.
Differential RF input/output. See
Typical Application
on page 12 for recom-
mended antenna hookup. Each of these pins must be DC grounded, 20 k or
less
FIFO status indicator bit
Ground connection
V
DD
for the digital interface
Enable input for SPI, active low. Also used to bring device out of sleep state.
Transmit/receive packet status indicator bit
Clock input for SPI interface
Data input for the SPI bus
Data output (tristate when not active)
RST_n Low: Chip shutdown to conserve power. Register values lost
RST_n High: Turn on chip, registers restored to default value
Unregulated input voltage to the on-chip low drop out (LDO) voltage regulator
+1.8 V output from on-chip LDO. Connect to all V
DD
pins, do not connect to
external loads.
Output of the crystal oscillator gain block
Input to the crystal oscillator gain block
Document Number: 001-61351 Rev. *K
Page 4 of 40
Not recommended for new designs
10
11
12
7
8
9
CYRF8935
Functional Overview
The CYRF8935 RF transceiver can add wireless capability to a
wide variety of applications.
The product is a low-cost, fully-integrated CMOS RF transceiver,
GFSK data modem, and packet framer, optimized for use in the
2.4-GHz ISM band. It contains transmit, receive, RF synthesizer,
and digital modem functions, with few external components. The
transmitter supports digital power control. The receiver uses
extensive digital processing for excellent overall performance,
even in the presence of interference and transmitter
impairments.
The product transmits GFSK data at approximately 0-dBm
output power. Sigma-Delta PLL delivers high-quality DC-coupled
transmit data path.
The low-IF receiver architecture produces good selectivity and
image rejection, with typical sensitivity of –87 dBm or better on
most channels. Sensitivity on channels that are integer multiples
of the crystal reference oscillator frequency (12 MHz) may show
approximately 5 dB degradation. Digital RSSI values are
available to monitor channel quality.
T
VIN
V
IN
RST_n
Clock stable
BRCLK
SPI_SS
T
RPW
T
RSU
T
CMIN
Write Reg[27]=
0x4200
(not drawn to scale)
Clock unstable
On-chip transmit and receive FIFO registers are available to
buffer the data transfer with MCU. Over-the-air data rate is
always 1 Mbps even when connected to a slow, low-cost MCU.
Built-in CRC, FEC, data whitening, and automatic
retry/acknowledge are all available to simplify and optimize
performance for individual applications.
Power-on and Register Initialization Sequence
For proper initialization at power up, V
IN
must ramp up at the
minimum overall ramp rate no slower than shown by T
VIN
speci-
fication in the following figure. During this time, the RST_n line
must track the V
IN
voltage ramp-up profile to within approxi-
mately 0.2 V. Since most MCU GPIO pins automatically default
to a high-Z condition at power up, it only requires a pull-up
resistor, as shown in
Figure 11
on page 14. When power is stable
and the MCU POR releases, and MCU begins to execute instruc-
tions, RST_n must then be pulsed low as shown in
Figure 2,
followed by writing Reg[27] = 0x4200. During or after this SPI
transaction, the State Machine status can be read to confirm
FRAMER_ST= 1, indicating a proper initialization.
Figure 2. Power-on and Register Programming Sequence
SPI Activity
Table 2. Initialization Timing Requirements
Timing Parameter
T
RSU
T
RPW
T
CMIN
T
VIN
Min
–
1
3
–
Max
20
10
–
6.5
Unit
ms
µs
ms
ms/V
2 < T
VIN
≤
6.5 [ms/V]
Notes
Reset setup time necessary to ensure
complete reset
Reset pulse width necessary to ensure complete reset
Minimum recommended crystal oscillator and APLL settling time
Maximum ramp time for V
IN
, measured from 0 to 100% of final voltage. For
example, if V
IN
= 3.3 V, the max ramp time is 6.5 × 3.3 = 21.45 ms. If V
IN
=
1.9 V, the max ramp time = 6.5 × 1.9 = 12.35 ms.
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After RST_n transitions from 0 to 1, BRCLK
[3]
begins running at 12-MHz clock.
After register initialization, CYRF8935 is ready to transmit or receive.
Note
3. BRCLK signal is available on bare die only, not packaged parts.
Document Number: 001-61351 Rev. *K
Page 5 of 40
Not recommended for new designs
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