February 2007
AS6C62256
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Description
Initial Issue
Revision of Supply current ISB1 – page 3
Commercial temp 20 µA
Industrial temp 30 µA
Revision of Alliance Memory address
Issue Date
February 2007
March 26, 2013
March 26, 2013
Rev 1.2
Further Revision of Supply current - page 3
Commercial temp 15 µA
Industrial temp 30 µA
IdR (data-retention current) to be 20uA
- page 7
March 23, 2016
March 23,2016 v1.2
Alliance Memory Inc.
Page 0 of 12
February 2007
®
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Access time : 55ns
Low power consumption:
Operation current :
15mA (TYP.), V
CC
= 3.0V
Standby current :
1µ A (TYP.), V
CC
= 3.0V
Wide range power supply : 2.7 ~ 5.5V
Fully Compatible with all Competitors 5V product
Fully Compatible with all Competitors 3.3V product
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage :1.5V (MIN.)
All products ROHS Compliant
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mm x 13.4mm sTSOP
GENERAL DESCRIPTION
The AS6C62256 is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The AS6C62256 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The AS6C62256 operates with wide range power
supply 2.7 ~ 5.5V
.
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
Vcc
Vss
A0 - A14
DQ0 – DQ7
DECODER
32Kx8
MEMORY ARRAY
CE#
WE#
OE#
V
CC
V
SS
A0-A14
DQ0-DQ7
I/O DATA
CIRCUIT
COLUMN I/O
CE#
WE#
OE#
CONTROL
CIRCUIT
March 23,2016 v1.2
Alliance Memory Inc.
Page 1 of 12
February 2007
®
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
28
27
26
25
Vcc
WE#
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
OE#
A11
A9
A8
A13
WE#
Vcc
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
AS6C62256
PDIP/SOP
5
6
7
8
9
10
11
12
13
14
24
23
22
21
20
19
18
17
16
15
AS6C62256
sTSOP
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
T
SOLDER
-40 to 85(I grade)
-65 to 150
1
50
260
RATING
-0.5 to 7.0
0 to 70(C grade)
UNIT
V
ºC
ºC
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
ºC
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
L
L
L
OE#
X
H
L
X
WE#
X
H
H
L
I/O OPERATION
High-Z
High-Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
,I
SB1
I
CC
,I
CC1
I
CC
,I
CC1
I
CC
,I
CC1
H = V
IH
, L = V
IL
, X = Don't care.
March 23,2016 v1.2
Alliance Memory Inc.
Page 2 of 12
February 2007
®
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
V
CC
*1
Input High Voltage
V
IH
*2
Input Low Voltage
V
IL
Input Leakage Current
I
LI
V
CC
>=
V
IN
>=
V
SS
Output Leakage
V
CC
>=
V
OUT
>=
V
SS
,
I
LO
Current
Output Disabled
Output High Voltage
V
OH
I
OH
= -1mA
Output Low Voltage
V
OL
I
OL
= 2mA
I
CC
Average Operating
Power supply Current
I
CC1
Standby Power
Supply Current
I
SB
I
SB1
Cycle time = Min.
CE# = V
IL
, I
I/O
= 0mA
-55
MIN.
2.7
2.4
V
- 0.5
-1
-1
2.4
-
-
TYP.
3.3
-
-
-
-
3.0
-
15
*5
MAX.
5.5
V
CC
+0.5
0.6
1
1
-
0.4
45
UNIT
V
V
V
µA
µA
V
V
mA
.
mA
mA
µA
µA
Cycle time = 1µs
CE#
≦
0.2V and I
I/O
= 0mA
other pins at 0.2V or V
CC
-0.2V
CE# = V
IH
-C
CE#
> =
V
CC
- 0.2V
Others at 0.2V or Vcc-0.2V
-I
-
-
-
-
3
1
1
1
10
3
*4
15
*4
30
Notes: C = Commercial Temperature I = Industrial Temperature
1. V
IH
(max) = V
CC
+ 3.0V for pulse width less than 10ns.
2. V
IL
(min) = V
SS
- 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. 10µA for special request
5. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at V
CC
= V
CC
(TYP.) and T
A
= 25ºC
CAPACITANCE
(T
A
= 25
?
, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to V
CC
- 0.2V
3ns
1.5V
C
L
= 50pF + 1TTL, I
OH
/I
OL
= -1mA/2mA
March 23,2016 v1.2
Alliance Memory Inc.
Page 3 of 12
February 2007
®
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM
t
RC
t
AA
t
ACE
t
OE
t
CLZ
*
t
OLZ
*
t
CHZ
*
t
OHZ
*
t
OH
AS6C62256-55
MIN
MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
*
t
WHZ
*
*These parameters are guaranteed by device characterization, but not production tested.
AS6C62256-55
MIN.
MAX.
55
-
50
-
50
-
0
-
45
-
0
-
25
-
0
-
5
-
-
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
March 23,2016 v1.2
26/MAR/13, v1.1
Alliance Memory Inc.
Page
4
of 12
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