19-2263; Rev 1; 4/06
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX1186
General Description
The MAX1186 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully-differential wideband track-
and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1186 is optimized for low-power, high
dynamic performance applications in imaging, instru-
mentation, and digital communication applications. This
ADC operates from a single 2.7V to 3.6V supply, con-
suming only 105mW while delivering a typical signal-to-
noise ratio (SNR) of 59.4dB at an input frequency of
20MHz and a sampling rate of 40Msps. Digital outputs
A and B are updated alternating on the rising (CHA)
and the falling (CHB) edge of the clock. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1186 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADCs. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1186 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output for-
mat can be set to two’s complement or straight offset
binary through a single control pin. The device provides
for a separate output power supply of 1.7V to 3.6V for
flexible interfacing. The MAX1186 is available in a
7mm x 7mm, 48-pin TQFP-EP package, and is speci-
fied for the extended industrial (-40°C to +85°C) tem-
perature range.
Pin-compatible, nonmultiplexed, high-speed versions of
the MAX1186 are also available. Please refer to the
MAX1180 data sheet for 105Msps, the MAX1181 data
sheet for 80Msps, the MAX1182 data sheet for 65Msps,
the MAX1183 data sheet for 40Msps, and the MAX1184
data sheet for 20Msps. For a pin-compatible lower
speed version (20Msps) of the MAX1186, please refer
to the MAX1185 data sheet.
Features
o
Single 3V Operation
o
Excellent Dynamic Performance:
59.4dB SNR at f
IN
= 20MHz
72dBc SFDR at f
IN
= 20MHz
o
Low Power:
35mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
o
0.02dB Gain and 0.25° Phase Matching
o
Wide ±1V
P-P
Differential Analog Input Voltage
Range
o
400MHz, -3dB Input Bandwidth
o
On-Chip 2.048V Precision Bandgap Reference
o
Single 10-Bit Bus for Multiplexed, Digital Outputs
o
User-Selectable Output Format—Two’s
Complement or Offset Binary
o
48-Pin TQFP Package with Exposed Paddle For
Improved Thermal Dissipation
Ordering Information
PART
MAX1186ECM
MAX1186ECM+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
48 TQFP-EP*
48 TQFP-EP*
PKG
CODE
C48E-7
C48E-7
+Denotes
lead-free package.
*EP
= Exposed paddle.
Pin-Compatible Versions table at end of data sheet.
Pin Configuration
REFN
REFP
REFIN
REFOUT
D9A/B
D8A/B
D7A/B
D6A/B
D5A/B
D4A/B
D3A/B
41
40
39
38
48
47
46
45
44
43
42
COM
V
DD
GND
INA+
INA-
V
DD
GND
INB-
INB+
GND
V
DD
CLK
37
D2A/B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
D1A/B
D0A/B
OGND
OV
DD
OV
DD
OGND
A/B
N.C.
N.C.
N.C.
N.C.
N.C.
Applications
High-Resolution Imaging
I/Q Channel Digitization
Multichannel IF Sampling
Instrumentation
Video Application
Ultrasound
MAX1186
30
29
28
27
EP
26
25
GND
V
DD
V
DD
GND
T/B
SLEEP
PD
OE
N.C.
N.C.
N.C.
48 TQFP-EP
Functional Diagram appears at end of data sheet.
NOTE:
THE PIN 1 INDICATOR FOR LEAD-FREE
PACKAGES IS REPLACED BY A "+" SIGN.
________________________________________________________________
Maxim Integrated Products
N.C.
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX1186
ABSOLUTE MAXIMUM RATINGS
V
DD
, OV
DD
to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN, COM,
CLK to GND............................................-0.3V to (V
DD
+ 0.3V)
OE,
PD, SLEEP, T/B, D9A/B–D0A/B,
A/B to OGND .......................................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP-EP (derate 30.4mW/°C
above +70°C).........................................................2430mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3V, OV
DD
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential w.r.t. COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Differential Input Voltage
Range
Common-Mode Input Voltage
Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS
Signal-to-Noise Ratio
(Note 3)
Signal-to-Noise and Distortion
(Note 3)
Spurious-Free Dynamic Range
(Note 3)
SNR
SINAD
SFDR
f
INA or B
= 7.5MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 7.5MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 7.5MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
57.3
56.8
57
56.5
64
64
59.5
59.4
59.4
59.2
74
72
dB
dB
dBc
f
CLK
CHA
CHB
40
5
5.5
MHz
Clock
cycles
V
DIFF
V
CM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±1
V
DD
/ 2
±
0.5
100
5
V
V
kΩ
pF
INL
DNL
f
IN
= 7.5MHz
f
IN
= 7.5MHz, no missing codes guaranteed
10
±0.5
±0.25
<
±1
0
±1.7
±1.0
±2.3
±2
Bits
LSB
LSB
% FS
% FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential w.r.t. COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Total Harmonic Distortion
(First 4 Harmonics) (Note 3)
Third-Harmonic Distortion
(Note 3)
Intermodulation Distortion
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
Differential Gain
Differential Phase
Output Noise
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
BUFFERED EXTERNAL REFERENCE (V
REFIN
= 2.048V)
REFIN Input Voltage
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Differential Reference Output
Voltage Range
REFIN Resistance
V
REFIN
V
REFP
V
REFN
∆V
REF
R
REFIN
∆V
REF
= V
REFP
- V
REFN
0.95
2.048
2.012
0.988
1.024
> 50
1.10
V
V
V
V
MΩ
REFOUT
TC
REF
2.048
±3%
60
1.25
V
ppm/°C
mV/mA
INA+ = INA- = INB+ = INB- = COM
FPBW
t
AD
t
AJ
For 1.5x full-scale input
SYMBOL
THD
HD3
IMD
CONDITIONS
f
INA or B
= 7.5MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 7.5MHz
f
INA or B
= 20MHz
f
INA or B
= 11.6066MHz at -6.5dBFS
f
INA or B
= 13.3839MHz at -6.5dBFS (Note 4)
Input at -20dBFS, differential inputs
Input at -0.5dBFS, differential inputs
MIN
TYP
-72
-71
-74
-72
-76
500
400
1
2
2
±1
±0.25
0.2
MAX
-64
-63
UNITS
dBc
dBc
dBc
MHz
MHz
ns
ps
RMS
ns
%
Degrees
LSB
RMS
MAX1186
_______________________________________________________________________________________
3
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX1186
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential w.r.t. COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink
Current
Maximum REFN Source Current
Maximum REFN Sink Current
SYMBOL
I
SOURCE
I
SINK
I
SOURCE
I
SINK
R
REFP
,
R
REFN
∆V
REF
V
COM
V
REFP
V
REFN
Measured between REFP and COM, and
REFN and COM
∆V
REF
= V
REFP
- V
REFN
CONDITIONS
MIN
TYP
5
-250
250
-5
MAX
UNITS
mA
µA
µA
mA
UNBUFFERED EXTERNAL REFERENCE (V
REFIN
= GND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
Differential Reference Input
Voltage
COM Input Voltage
REFP Input Voltage
REFN Input Voltage
4
1.024
±10%
V
DD
/ 2
±10%
V
COM
+
∆V
REF
/ 2
V
COM
-
∆V
REF
/ 2
0.8
V
DD
0.8
x OV
DD
0.2
x V
DD
0.2
x OV
DD
0.1
V
IH
= OV
DD
or V
DD
(CLK)
V
IL
= 0
5
I
SINK
= -200µA
I
SOURCE
= 200µA
OE
= OV
DD
OE
= OV
DD
5
OV
DD
- 0.2
±10
0.2
±5
±5
V
µA
pF
V
V
µA
pF
kΩ
V
V
V
V
DIGITAL INPUTS (CLK, PD,
OE,
SLEEP, T/B)
CLK
Input High Threshold
V
IH
PD,
OE,
SLEEP, T/B
CLK
Input Low Threshold
V
IL
PD,
OE,
SLEEP, T/B
Input Hysteresis
Input Leakage
Input Capacitance
Output-Voltage Low
Output-Voltage High
Three-State Leakage Current
Three-State Output Capacitance
V
HYST
I
IH
I
IL
C
IN
V
OL
V
OH
I
LEAK
C
OUT
V
V
DIGITAL OUTPUTS (D0A/B–D9A/B, A/B)
4
_______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX1186
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential w.r.t. COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
V
DD
OV
DD
Operating, f
INA or B
= 20MHz at -0.5dBFS
I
VDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, C
L
= 15pF, f
INA or B
= 20MHz at
-0.5dBFS
Output Supply Current
I
OVDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA or B
= 20MHz at -0.5dBFS
Power Dissipation
PDISS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
CLK Fall to CHB Output Data
Valid
Clock Rise/Fall to A/B Rise/Fall
Time
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
t
DOA
t
DOB
t
DA/B
t
ENABLE
t
DISABLE
t
CH
t
CL
t
WAKE
Figure 4
Figure 4
Figure 3, clock period: 25ns
Figure 3, clock period: 25ns
Wake-up from sleep mode (Note 6)
Wake-up from shutdown (Note 6)
f
INA or B
= 20MHz at -0.5dBFS
f
INA or B
= 20MHz at -0.5dBFS
f
INA or B
= 20MHz at -0.5dBFS
Figure 3 (Note 5)
Figure 3 (Note 5)
5
5
6
10
1.5
12.5
±3.8
12.5
±3.8
0.41
1.5
-70
0.02
0.25
±0.2
8
8
ns
ns
ns
ns
ns
ns
ns
µs
PSRR
Offset
Gain
2.7
1.7
3.0
2.5
35
2.8
1
9
100
2
105
8.4
3
±0.2
±0.1
45
10
150
15
3.6
3.6
50
V
V
mA
µA
mA
µA
mW
µW
mV/V
%/V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
dB
dB
Degrees
Note 1:
Equivalent dynamic performance is obtainable over full OV
DD
range with reduced C
L
.
Note 2:
Specifications at
≥
+25°C are guaranteed by production test and < +25°C guaranteed by design and characterization.
Note 3:
SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a ±1.024V full-scale
input voltage range.
Note 4:
Intermodulation distortion power of the intermodulation products relative to the individual carrier. This number is 6dB or bet-
ter, if referenced to the two-tone envelope.
Note 5:
Digital outputs settle to V
IH
and V
IL
. Parameter guaranteed by design.
Note 6:
With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
_______________________________________________________________________________________
5
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