FemtoClock
®
Zero Delay Buffer/ Clock
Generator for PCI Express™ and Ethernet
General Description
The ICS8714008I is Zero-Delay Buffer/Frequency Multiplier with
eight differential HCSL output pairs, and uses external feedback
(differential feedback input and output pairs) for “zero delay” clock
regeneration. In PCI Express and Ethernet applications, 100MHz
and 125MHz are the most commonly used reference clock
frequencies and each of the eight output pairs can be independently
set for either 100MHz or 125MHz. With an output frequency range of
98MHz to 165MHz, the device is also suitable for use in a variety of
other applications such as Fibre Channel (106.25MHz) and XAUI
(156.25MHz). The M-LVDS Input/Output pair is useful in backplane
applications when the reference clock can either be local (on the
same board as the ICS8714008I) or remote via a backplane
connector. In output mode, an input from a local reference clock
applied to the CLK, nCLK input pins is translated to M-LVDS and
driven out to the MLVDS, nMLVDS pins. In input mode, the internal
M-LVDS driver is placed in High-impedance state using the
OE_MLVDS pin and MLVDS, nMLVDS pin then becomes an input
(e.g. from a backplane).
The ICS8714008I uses very low phase noise FemtoClock
technology, thus making it ideal for such applications as PCI Express
Generation 1, 2 and 3 as well as for Gigabit Ethernet, Fibre Channel,
and 10 Gigabit Ethernet. It is packaged in a 56-VFQFN package
(8mm x 8mm).
ICS8714008I
DATASHEET
Features
•
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•
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•
•
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Eight 0.7V differential HCSL output pairs, individually selectable
for 100MHz or 125MHz for PCIe and Ethernet applications
One differential clock input pair CLK, nCLK can accept the
following differential input levels: LVPECL, LVDS, M-LVDS,
LVHSTL, HCSL
One M-LVDS I/O pair (MLVDS, nMLVDS)
Output frequency range: 98MHz - 165MHz
Input frequency range: 19.6MHz - 165MHz
VCO range: 490MHz - 660MHz
PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s)
jitter compliant
External feedback for “zero delay” clock regeneration
RMS phase jitter @ 125MHz (1.875MHz – 20MHz):
0.59ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Lead-free (RoHs 6) packaging
Pin Assignment
PDIV0
nCLK
CLK
V
DDA
QDIV4
QDIV5
QDIV6
QDIV7
Q0
nQ0
V
DD
Q1
PDIV1
nQ1
56 55 54 53 52 51 50 49 48 47 46 45 44 43
V
DD
OE_MLVDS
MLVDS
nMLVDS
GND
PLL_SEL
V
DD
nc
FBO_DIV
MR
OE0
OE1
OE2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FBI_DIV0
42
41
40
39
38
37
36
35
34
33
32
31
30
29
17 18
nFBIN
FBIN
V
DD
Q2
nQ2
Q3
nQ3
V
DD
Q4
nQ4
Q5
nQ5
FBOUT
nFBOUT
V
DD
IREF
21
QDIV0
QDIV1
24 25
Q7
nQ7
27 28
Q6
nQ6
ICS8714008I
56-Lead VFQFN
8mm x 8mm x 0.925mm package body
4.5mm x 5.2mm ePad size
K Package
Top View
ICS8714008DKI REVISION A NOVEMBER 25, 2013
1
©2013 Integrated Device Technology, Inc.
ICS8714008I DATA SHEET
FEMTOCLOCK
®
ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS
TM
AND ETHERNET
Block Diagram
MR
1
PDIV1
PDIV0
Pulldown
Pulldown
Pulldown
QDIV0
0 ÷4 (default)
1 ÷5
Q0
nQ0
3
OE2:0 (PU:PU)
QDIV0 (PD)
CLK
nCLK
MR
1
OE_MLVDS
MLVDS
nMLVDS
Pulldown
PU/PD
Pulldown
Pullup
PDIV1:0
00 ÷4 (default)
01 ÷5
10 ÷8
11 ÷1
0
8 total HCSL Output pairs
PD
FBI_DIV1
FBI_DIV0
Pullup
Pullup
VCO
490-660MHz
1
QDIV7 (PD)
FBI_DIV1:0
00 ÷1
01 ÷2
10 ÷4
11 ÷5 (default)
QDIV7
0 ÷4 (default)
1 ÷5
Q7
nQ7
FBIN
nFBIN
Pulldown
PU/PD
MR
1
Pulldown
FBO_DIV
0 ÷4 (default)
1 ÷5
FBO_DIV (PD)
FBOUT
nFBOUT
IREF
PLL_SEL
1
Pullup
MR
Pulldown
One Master Reset pin (MR) is used to reset all the internal dividers, but the MR lines are not drawn as all tied together to reduce control line clutter, making the block diagram
easier to read.
PU means internal pull-up resistor on pin (power-up default is HIGH if not externally driven)
PD means internal pull-down resistor on pin (power-up default is LOW if not externally driven)
1
ICS8714008DKI REVISION A NOVEMBER 25, 2013
2
©2013 Integrated Device Technology, Inc.
ICS8714008I DATA SHEET
FEMTOCLOCK
®
ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS
TM
AND ETHERNET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 7, 30, 37,
42, 45
Name
V
DD
Power
Type
Description
Core supply pins.
Active High Output Enable. When HIGH, the M-LVDS output driver is active
and provides a buffered copy of reference clock applied the CLK, nCLK
input to the MLVDS, nMLVDS output pins. The MLVDS, nMLVDS
frequency equals the CLK, nCLK frequency divided by the PDIV Divider
value (selectable ÷1, ÷4, ÷5, ÷8). When LOW, the M-LVDS output driver is
placed into a High-impedance state and the MLVDS, nMLVDS pins can
accept a differential input. LVCMOS/LVTTL interface levels.
Non-Inverting M-LVDS input/output. The input/output state is determined by
the OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and
drives the non-inverting M-LVDS output. When OE_MLVDS = LOW, this pin
is an input and can accept the following differential input levels: M-LVDS,
LVDS, LVPECL, HSTL, HCSL.
Inverting M-LVDS input/output. The input/output state is determined by the
OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives
the inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input
and can accept the following differential input levels: M-LVDS, LVDS,
LVPECL, HSTL, HCSL.
Power supply ground.
PLL select. Determines if the PLL is in bypass or enabled mode (default). In
enabled mode, the output frequency = VCO frequency/QDIV divider. In
bypass mode, the output frequency = reference clock frequency/(PDIV
*QDIV). LVCMOS/LVTTL interface levels.
No internal connection.
Pulldown
Output Divider Control for the feedback output pair, FBOUT, nFBOUT.
Determines if the output divider = ÷4 (default), or ÷5. Refer to Table 3D.
LVCMOS/LVTTL interface levels.
Active High master reset. When logic HIGH, the internal dividers are reset
causing all the true outputs Qx to drive High-impedance. Note that assertion
of MR overrides the OE[2:0] control pins and all outputs are disabled. When
logic LOW, the internal dividers are enabled and the state of the outputs are
determined by OE[2:0]. MR must be asserted on power-up to ensure
outputs phase aligned. LVCMOS/LVTTL interface levels.
Output Enable. Together with OE1 and OE2, determines the output state of
the outputs with the default state: all output pairs switching. It should also be
noted that the feedback output pins (FBOUT, nFBOUT) are always
switching and are not affected by the state of OE[2:0]. Refer to Table 3B for
truth table. LVCMOS/LVTTL Interface levels.
Output Enable. Together with OE0 and OE2, determines the output state of
the outputs with the default state: all output pairs switching. It should also be
noted that the feedback output pins (FBOUT, nFBOUT) are always
switching and are not affected by the state of OE[2:0]. Refer to Table 3B for
truth table. LVCMOS/LVTTL Interface levels.
Output Enable. Together with OE0 and OE1, determines the output state of
the outputs with the default state: all output pairs switching. It should also be
noted that the feedback output pins (FBOUT, nFBOUT) are always
switching and are not affected by the state of OE[2:0]. Refer to table 3B for
truth table. LVCMOS/LVTTL Interface levels.
2
OE_MLVDS
Input
Pullup
3
MLVDS
I/O
4
nMLVDS
I/O
5, 14, 19
GND
Power
6
PLL_SEL
Input
Pullup
8, 26
9
nc
FBO_DIV
Unused
Input
10
MR
Input
Pulldown
11
OE0
Input
Pullup
12
OE1
Input
Pullup
13
OE2
Input
Pullup
ICS8714008DKI REVISION A NOVEMBER 25, 2013
3
©2013 Integrated Device Technology, Inc.
ICS8714008I DATA SHEET
FEMTOCLOCK
®
ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS
TM
AND ETHERNET
Table 1. Pin Descriptions
Number
15
Name
FBI_DIV0
Input
Type
Pullup
Description
Feedback Input Divide Select 0. Together with FBI_DIV1, determines the
feedback input divider value. Refer to Table 3C.
LVCMOS/LVTTL interface levels.
Feedback Input Divide Select 1. Together with FBI_DIV0, determines the
feedback input divider value. Refer to Table 3C.
LVCMOS/LVTTL interface levels.
Inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.”
Output Divider Control for Q0, nQ0. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q1, nQ1. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q2, nQ2. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q3, nQ3. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
An external fixed resistor from this pin to ground is needed to provide a
reference current for the differential HCSL outputs. A resistor value of 475
provides an HCSL voltage swing of approximately 700mV.
Differential feedback output pair. The feedback output pair always switches
independent of the output enable settings on the OE[2:0] pins.
HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Pulldown
Pulldown
Pulldown
Pulldown
Output Divider Control for Q7, nQ7. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q6, nQ6. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q5, nQ5. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q4, nQ4. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown
Non-inverting differential clock input.
Accepts LVPECL, HCSL, LVDS, M-LVDS and HSTL input levels.
16
FBI_DIV1
Input
Pullup
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
17
18
20
21
22
23
24, 25
27, 28
29
nFBIN
FBIN
QDIV0
QDIV1
QDIV2
QDIV3
Q7, nQ7
Q6, nQ6
IREF
Input
Input
Input
Input
Input
Input
Output
Output
Input
31,
32
33, 34
35, 36
38, 39
40, 41
43, 44
46, 47
48
49
50
51
52
53
nFBOUT,
FBOUT
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
QDIV7
QDIV6
QDIV5
QDIV4
V
DDA
CLK
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Power
Input
ICS8714008DKI REVISION A NOVEMBER 25, 2013
4
©2013 Integrated Device Technology, Inc.
ICS8714008I DATA SHEET
FEMTOCLOCK
®
ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS
TM
AND ETHERNET
Table 1. Pin Descriptions
Number
54
55
56
Name
nCLK
PDIV0
PDIV1
Input
Input
Input
Type
Pullup/
Pulldown
Pulldown
Pulldown
Description
Inverting differential clock input.
Accepts LVPECL, HCSL, LVDS, M-LVDS and HSTL input levels.
Input Divide Select 0. Together with PDIV1 determines the input divider
value. Refer to Table 3F. LVCMOS/LVTTL Interface levels.
Input Divide Select 1. Together with PDIV0 determines the input divider
value. Refer to Table 3F. LVCMOS/LVTTL Interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS8714008DKI REVISION A NOVEMBER 25, 2013
5
©2013 Integrated Device Technology, Inc.
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