1. This parameter is measured at characterization but not tested
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Not to exceed 3.6V.
RECOMMENDED OPERATING RANGE
Symbol
T
A
V
DD
Description
Ambient Operating Temperature
Internal Power Supply Voltage
Min.
–40
2.3
Typ.
+25
2.5
Max.
+85
2.7
Unit
°C
V
PIN DESCRIPTION
Symbol
A
[1:2]
A
[1:2]
I/O
I
I
Type
Adjustable
(1,4)
Adjustable
(1,4)
Description
Clock input. A
[1:2]
is the "true" side of the differential clock input.
Complementary clock inputs.
A
[1:2]
is the complementary side of A
[1:2].
For LVTTL single-ended operation,
A
[1:2]
should be set
to the desired toggle voltage for A
[1:2]
:
3.3V LVTTL V
REF
= 1650mV
2.5V LVTTL V
REF
= 1250mV
Gate control for differential outputs Q
1
and
Q
1
through Q
6
and
Q
6
. When
G
is LOW, the differential outputs are active. When
G
is HIGH, the differential outputs are asynchronously driven to the level designated by GL
(2)
.
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"
outputs disable LOW and "complementary" outputs disable HIGH.
Clock outputs
Complementary clock outputs
Reference clock select. When LOW, selects A
2
and
A
2
. When HIGH, selects A
1
and
A
1
.
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled.
Both "true" and "complementary" outputs will pull to V
DD
. Set HIGH for normal operation.
(3)
Power supply for the device core and inputs
Power supply return for all power
No connect; recommended to connect to GND
G
GL
Qn
Qn
SEL
PD
V
DD
GND
NC
I
I
O
O
I
I
LVTTL
LVTTL
LVDS
LVDS
LVTTL
LVTTL
PWR
PWR
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be
able to tolerate them in down stream circuitry.
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting
PD.
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL
(1)
RANG
Symbol
Parameter
Input Characteristics
I
IH
Input HIGH Current
I
IL
Input LOW Current
V
IK
Clamp Diode Voltage
V
IN
DC Input Voltage
V
IH
DC Input HIGH
V
IL
DC Input LOW
V
THI
DC Input Threshold Crossing Voltage
V
REF
Single-Ended Reference Voltage
(3)
Test Conditions
V
DD
= 2.7V
V
DD
= 2.7V
V
DD
= 2.3V, I
IN
= -18mA
Min.
—
—
—
- 0.3
1.7
—
—
—
—
Typ.
(2)
—
—
- 0.7
—
—
—
V
DD
/2
1.65
1.25
Max
±5
±5
- 1.2
+3.6
—
0.7
—
—
—
Unit
μA
V
V
V
V
V
V
3.3V LVTTL
2.5V LVTTL
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at V
DD
= 2.5V, +25°C ambient.
3. For A
[1:2]
single-ended operation,
A
[1:2]
is tied to a DC reference voltage.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR
DIFFERENTIAL INPUTS
(1)
Symbol
Parameter
Input Characteristics
I
IH
Input HIGH Current
I
IL
Input LOW Current
V
IK
Clamp Diode Voltage
V
IN
DC Input Voltage
V
DIF
DC Differential Voltage
(3)
V
CM
DC Common Mode Input Voltage
(4)
Test Conditions
V
DD
= 2.7V
V
DD
= 2.7V
V
DD
= 2.3V, I
IN
= -18mA
Min.
—
—
—
- 0.3
0.1
0.05
Typ.
(2)
—
—
- 0.7
—
—
—
Max
±5
±5
- 1.2
+3.6
—
V
DD
Unit
μA
V
V
V
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at V
DD
= 2.5V, +25°C ambient.
3. V
DIF
specifies the minimum input differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is the "complement" input level. The DC differential voltage
must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state.
4. V
CM
specifies the maximum allowable range of (V
TR
+ V
CP
) /2.
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
RANGE FOR LVDS
(1)
Symbol
Parameter
Output Characteristics
V
OT
(+)
Differential Output Voltage for the True Binary State
V
OT
(-)
Differential Output Voltage for the False Binary State
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the V
DIF
(AC) specification
under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the V
X
specification under actual
use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
V
DIF
V
X
D
H
V
THI
t
R
, t
F
Parameter
Input Signal Swing
(1)
Differential Input Signal Crossing Point
Duty Cycle
Input Timing Measurement Reference Level
(3)
Input Signal Edge Rate
(4)
(2)
Value
1
900
50
Crossing Point
2
Units
V
mV
%
V
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the V
DIF
(AC) specification
under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the V
X
specification under actual
use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL (2.5V) AND
LVPECL (3.3V)
Symbol
V
DIF
V
X
D
H
V
THI
t
R
, t
F
Parameter
Input Signal Swing
(1)
Differential Input Signal Crossing Point
Duty Cycle
Input Timing Measurement Reference Level
(3)
Input Signal Edge Rate
(4)
(2)
Value
732
LVEPECL
LVPECL
1082
1880
50
Crossing Point
2
Units
mV
mV
%
V
V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the V
DIF
(AC) specification
under actual use conditions.
2. 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This
device meets the V
X
specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
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