2Gb DDR2 - AS4C256M8D2
Revision History
2Gb DDR2
-AS4C256M8D2
-
60
ball FBGA PACKAGE
Revision
Rev 1.0
Details
Preliminary datasheet
Date
September 2014
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
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Rev.1.0
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2Gb DDR2 - AS4C256M8D2
Features
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High speed data transfer rates with system frequency up to
400
MHz
8 internal banks for concurrent operation
4-bit prefetch architecture
Programmable CAS Latency: 3, 4 ,5 , 6 and 7
Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6
Write Latency = Read Latency -1
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 us at -40
o
C
≤
Tcase
≤
85
o
C,
3.9 us at 85
o
C < Tcase
≤
105
o
C
ODT (On-Die Termination)
Weak Strength Data-Output Driver Option
Bidirectional differential Data Strobe (Single-ended data-
strobe is an optional feature)
On-Chip DLL aligns DQ and DQs transitions with CK transi-
tions
DQS can be disabled for single-ended data strobe
Read Data Strobe (RDQS) supported (x8 only)
Differential clock inputs CK and CK
JEDEC Power Supply 1.8V ± 0.1V
VDDQ =1.8V ± 0.1V
Available in 60-ball FBGA for x8 component
RoHS compliant
tRAS lockout supported
Description
The
AS4C256M8D2
is a eight bank DDR DRAM organized as
8 banks x 32Mbit x 8. The
AS4C256M8D2
achieves high
speed data transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data
to a system clock.
The chip is designed to comply with the following key DDR2
SDRAM features:(1) posted CAS with additive latency, (2) write
latency = read latency-1, (3) On Die Termination.
All of the control, address, circuits are synchronized with the
positive edge of an externally supplied clock. I/O s are synchro-
nized with a pair of bidirectional strobes (DQS, DQS) in a source
synchronous fashion.
Operating the eight memory banks in an interleaved fashion
allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data
rate is possible depending on burst length, CAS latency and
speed grade of the device.
Table 1:
Table 1. Speed Grade Information
Speed Grade
DDR2-800
Clock Frequency
400 MHz
CAS Latency
5
t
RCD
(ns)
12.5
t
RP
(ns)
12.5
Table 2. Ordering Information
Product part No
Org
Temperature
Package
AS4C256M8D2-25BCN 256M x 8
AS4C256M8D2-25BIN
256M x 8
Commercial (Extended)
60-ball FBGA
0°C to
+95°C
Industrial
60-ball FBGA
-40°C to
+95°C
(Extended)
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2Gb DDR2 - AS4C256M8D2
256MX8 DDR2 PIN CONFIGURATION
<Top View>
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2Gb DDR2 - AS4C256M8D2
Signal Pin Description
Pin
CK, CK
CKE
Type
Input
Input
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CK.
Activates the CK signal when high and deactivates the CK signal when low, thereby initiates either the
Power Down mode, or the Self Refresh mode.
CS enables the command decoder when low and disables the command decoder when high. When
the command decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be
executed by the SDRAM.
During a Bank Activate command cycle, A0-A14 defines the row address (RA0-RA14) when sampled
at the rising clock edge for x8.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled
at the rising clock edge.CAn depends on the SDRAM organization:
256M x 8 DDR CAn = CA9
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1, BA2 defines the
bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0, BA1and BA2 to control
which bank(s) to precharge. If A10 is high, all eight banks will be precharged simultaneously regardless
of state of BA0 , BA1 and BA2.
CS
Input
RAS, CAS, WE
Input
A0 - A14
Input
BA0-BA2
DQx
Input
Input/
Output
Input/
Output
Selects which bank is to be active.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQ0-DQ7 for x8 device.
Data Strobe, output with read data, input with write data. Edge-aligned with read data, centered in write
data. For x8 device, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read
timing. The data strobes DQS and RDQS may be used in single ended mode or paired with optional
complimentary signals DQS and RDQS to provide differential pair signaling to the system during both
reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals.
DM is an input mask signal for write data. Input data is masked when DM is sampled high along with
that input data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading is designed to match that of DQ and DQS pins.
For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
SSTL Reference Voltage for Inputs
Isolated power supply and ground for the DLL to provide improved noise immunity.
On Die Termination Enable. It enables termination resistance internal to the DRAM. ODT is applied to
each DQ, DQS, DQS, RDQS, RDQS and DM for x8 device. ODT will be ignored if EMRS disable the
function.
DQS, (DQS)
RDQS, (RDQS)
DM
Input
VDD, VSS
VDDQ, VSSQ
VREF
VDDL, VSSDL
ODT
Supply
Supply
Input
Supply
Input
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2Gb DDR2 - AS4C256M8D2
Simplified State Diagram
Initialization
Sequence
CKEL
OCD
calibration
SRF
PR
Setting
MRS
EMRS
Idle
MRS
All banks
precharged
CKEL
ACT
CKEH
Precharge
Power
Down
CKEL
REF
Refreshing
Self
Refreshing
CKEH
CKEL
CKEL
Active
Power
Down
CKEL
Activating
CKEL
Automatic Sequence
Command Sequence
CKEH
Bank
Active
Write
Write
WRA
Writing
RDA
Read
Write
Read
Read
Reading
WRA
RDA
Writing
with
Autoprecharge
PR, PRA
PR, PRA
PR, PRA
RDA
Reading
with
Autoprecharge
Precharging
CKEL = CKE low, enter Power Down
CKEH = CKE high, exit Power Down, exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
PR(A) = Precharge (All)
MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
Note: Use caution with this diagram. It is
intended
to provide a floorplan of the possible state transitions
and the commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured
in full detail.
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