• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Output frequency: 3.75MHz to 100MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 5V with TTL outputs
• 3 skew grades:
IDT5991A-2: t
SKEW0
<250ps
IDT5991A-5: t
SKEW0
<500ps
IDT5991A-7: t
SKEW0
<750ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 46mA I
OL
high drive outputs
• Low Jitter: <200ps peak-to-peak
• Outputs drive 50Ω terminated lines
Ω
• Pin-compatible with Cypress CY7B991
• Available in PLCC Package
IDT5991A
FEATURES:
DESCRIPTION:
The IDT5991A is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The IDT5991A has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals
that may be hard-wired to appropriate HIGH-MID-LOW levels.
The IDT5991A maintains Cypress CY7B991 compatibility while pro-
viding two additional features: Synchronous Output Enable (GND/sOE),
and Positive/Negative Edge Synchronization (V
CCQ
/PE). When the GND/
sOE
pin is held low, all the outputs are synchronously enabled (CY7B991
compatibility). However, if GND/sOE is held high, all the outputs except
3Q0 and 3Q1 are synchronously disabled.
Furthermore, when the V
CCQ
/PE is held high, all the outputs are syn-
chronized with the positive edge of the REF clock input (CY7B991 com-
patibility). When V
CCQ
/PE is held low, all the outputs are synchronized
with the negative edge of REF.
FUNCTIONAL BLOCK DIAGRAM
G ND/sO E
Skew
Select
3
3
1F1:0
V
CCQ
/PE
Skew
Select
REF
PLL
FB
3
FS
Skew
Select
3
3
3F1:0
3
3
2F1:0
1Q
0
1Q
1
2Q
0
2Q
1
3Q
0
3Q
1
Skew
Select
3
3
4F1:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
4Q
0
4Q
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2001
Integrated Device Technology, Inc.
AUGUST 2001
DSC 5843/1
IDT5991A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
TEST
V
CCQ
GND
3F
0
REF
2F
1
FS
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
I
T
J
29
28
27
26
25
24
23
22
21
2F
0
GND/sOE
1F
1
1F
0
V
CCN
1Q
0
1Q
1
GND
GND
Description
Supply Voltage to Ground
DC Input Voltage
Junction Temperature
Storage Temperature
Max
–0.5 to +7
–0.5 to +7
150
–65 to +150
Unit
V
V
°C
°C
4
3F
1
4F
0
4F
1
V
CCQ
/PE
V
CCN
4Q
1
4Q
0
GND
GND
5
6
7
8
9
10
11
12
13
14
3
2
1
32
31
30
T
STG
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
15
16
17
18
19
20
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
Description
Input Capacitance
Typ.
5
Max.
7
Unit
pF
V
CCN
V
CCN
3Q
0
3Q
1
FB
2Q
1
2Q
0
PLCC
TOP VIEW
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
GND/
sOE
(1)
Type
IN
IN
IN
IN
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
Summary Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q
0
and 3Q
1
) in a LOW state - 3Q
0
and 3Q
1
may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[
1:0
] pins act as output disable
controls for individual banks when nF[
1:0
] = LL. Set GND/sOE LOW for normal operation.
V
CCQ
/PE
nF[
1:0
]
FS
nQ[
1:0
]
V
CCN
V
CCQ
GND
IN
IN
IN
OUT
PWR
PWR
PWR
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)
Four banks of two outputs with programmable skew
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
NOTE:
1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless nF[
1:0
] = LL.
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit t
U
which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF
1:0
control pins. In order
2
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
1:0
control pins.
IDT5991A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
EXTERNAL FEEDBACK
By providing external feedback, the IDT5991A gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW
Timing Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(3)
Max Adjustment:
±9.09ns
±49º
±14%
Example 1, F
NOM
= 15MHz
Example 2, F
NOM
= 25MHz
Example 3, F
NOM
= 30MHz
Example 4, F
NOM
= 40MHz
Example 5, F
NOM
= 50MHz
Example 6, F
NOM
= 80MHz
t
U
= 1.52ns
t
U
= 0.91ns
t
U
= 0.76ns
—
—
—
±9.23ns
±83º
±23%
—
t
U
= 1.54ns
t
U
= 1.28ns
t
U
= 0.96ns
t
U
= 0.77ns
—
±9.38ns
±135º
±37%
—
—
—
t
U
= 1.56ns
t
U
= 1.25ns
t
U
= 0.78ns
ns
Phase Degrees
% of Cycle Time
1/(44 x F
NOM
)
15 to 35MHz
FS = MID
1/(26 x F
NOM
)
25 to 60MHz
FS = HIGH
1/(16 x F
NOM
)
40 to 100MHz
Comments
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on
input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q
1:0
, 2Q
1:0
, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided
output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6t
U
skew adjustment is possible and at the lowest F
NOM
value.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
LL
(1)
LM
LH
ML
MM
MH
HL
HM
HH
Skew (Pair #1, #2)
–4t
U
–3t
U
–2t
U
–1t
U
Zero Skew
1t
U
2t
U
3t
U
4t
U
Skew (Pair #3)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Divide by 4
Skew (Pair #4)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Inverted
(2)
NOTES:
1. LL disables outputs if TEST = MID and GND/sOE = HIGH.
2. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when V
CCQ
/PE = HIGH, GND/sOE disables pair #4 LOW when V
CCQ
/PE = LOW.
3
IDT5991A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
IDT5991A-5, -7
(Industrial)
Symbol
V
CC
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
4.5
-40
Max.
5.5
+85
IDT5991A-2
(Commercial)
Min.
4.75
0
Max.
5.25
+70
Unit
V
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(1)
Input MID Voltage
(1)
Input LOW Voltage
(1)
Input Leakage Current
(REF, FB Inputs Only)
I
3
I
PU
I
PD
V
OH
V
OL
I
OS
3-Level Input DC Current (TEST, FS, nF
1:0
)
Input Pull-Up Current (V
CCQ
/PE)
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
(2)
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
=
V
CC
or GND
V
CC
= Max.
Min.
2
—
V
CC
/2
−
0.5
V
CC
−
1
Max.
—
0.8
—
V
CC
/2+0.5
Unit
V
V
V
V
V
µA
—
—
HIGH Level
MID Level
LOW Level
—
—
—
—
—
2.4
—
—
—
1
±5
±200
±50
±200
±100
±100
—
—
0.45
V
IN
=
V
CC
V
IN
=
V
CC
/2
V
IN
= GND
V
CC
= Max., V
IN
= GND
V
CC
= Max., V
IN
=
V
CC
µA
µA
µA
V
V
mA
−
16mA
V
CC
= Min., I
OH
=
−
40mA
V
CC
= Min., I
OH
=
V
CC
= Min., I
OL
= 46mA
V
CC
= Max., V
O
= GND
−
250
NOTES:
1. These inputs are normally wired to V
CC
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
CC
/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limits are achieved.
2. This is to be measured at 25°C with 10:1 duty cycle, one output at a time, and one second maximum.
POWER SUPPLY CHARACTERISTICS
Symbol
I
CCQ
∆I
CC
I
CCD
I
TOT
Parameter
Quiescent Power Supply Current
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
Total Power Supply Current
Test Conditions
(1)
V
CC
= Max., TEST = MID, REF = LOW,
GND/sOE = LOW, All outputs unloaded
V
CC
= Max., V
IN
= 3.4V
V
CC
= Max., C
L
= 0pF
V
CC
= 5V, F
REF
= 20MHz, C
L
= 240pF
(1)
V
CC
= 5V, F
REF
= 33MHz, C
L
= 240pF
(1)
V
CC
= 5V, F
REF
= 66MHz, C
L
= 240pF
(1)
NOTE:
1. For eight outputs, each loaded with 30pF.
Typ.
(2)
10
0.4
100
43
63
117
Max.
40
1.5
160
—
—
—
Unit
mA
mA
µA/MHz
mA
4
IDT5991A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
t
PWC
D
H
R
EF
Description
(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Reference Clock Input
Min.
—
3
10
3.75
Max.
10
—
90
100
Unit
ns/V
ns
%
MHz
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5991A-2
Symbol
F
NOM
t
RPWH
t
RPWL
t
U
t
SKEWPR
t
SKEW0
t
SKEW1
t
SKEW2
t
SKEW3
t
SKEW4
t
DEV
t
PD
t
ODCV
t
PWH
t
PWL
t
ORISE
t
OFALL
t
LOCK
t
JR
Parameter
VCO Frequency Range
REF Pulse Width HIGH
(1)
REF Pulse Width LOW
(1)
Programmable Skew Time Unit
Zero Output Matched-Pair Skew (xQ
0
, xQ
1
)
(1,2,3)
Zero Output Skew (All Outputs)
(1,4,5)
Output Skew
(Rise-Rise, Fall-Fall, Same Class Outputs)
(1,3)
Output Skew
(Rise-Fall, Nominal-Inverted, Divided-Divided)
(1,6)
Output Skew
(Rise-Rise, Fall-Fall, Different Class Outputs)
(1,6)
Output Skew
(Rise-Fall, Nominal-Divided, Divided-Inverted)
(1,2)
Device-to-Device Skew
(1,2,7)
REF Input to FB Propagation Delay
(1,9)
Output Duty Cycle Variation from 50%
(1)
Output HIGH Time Deviation from 50%
(1,10)
Output LOW Time Deviation from 50%
(1,11)
Output Rise Time
(1)
Output Fall Time
(1)
PLL Lock Time
(8)
Cycle-to-Cycle Output Jitter
(1)
RMS
Peak-to-Peak
—
—
0
0
—
—
1
1
—
—
—
0.75
0.25
1.2
2
2.5
1.2
1.2
0.5
25
200
—
—
0
0
—
—
1
1
—
—
—
1.25
0.5
1.2
2.5
3
1.5
1.5
0.5
25
200
—
—
0
0
—
—
1.5
1.5
—
—
—
1.65
0.7
1.2
3
3.5
2.5
2.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ms
ps
—
0.5
0.9
—
0.5
1
—
1.2
1.7
ns
—
0.25
0.5
—
0.5
0.7
—
0.7
1.2
ns
—
0.5
1
—
0.5
1.2
—
0.5
1.5
ns
—
—
—
0.05
0.1
0.25
0.2
0.25
0.5
3
3
—
—
Min.
Typ.
Max.
—
—
Min.
3
3
—
—
—
IDT5991A-5
Typ.
—
—
0.1
0.25
0.6
Max.
—
—
0.25
0.5
0.7
Min.
3
3
—
—
—
IDT5991A-7
Typ.
—
—
0.1
0.3
0.6
Max.
—
—
0.25
0.75
1
Unit
ns
ns
ns
ns
ns
See PLL Programmable Skew Range and Resolution Table
See Control Summary Table
−
0.25
−
1.2
—
—
0.15
0.15
—
—
—
−
0.5
−
1.2
—
—
0.15
0.15
—
—
—
−
0.7
−
1.2
—
—
0.15
0.15
—
—
—
NOTES:
1. All timing and jitter tolerances apply for F
NOM
> 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are loaded with the specified
load.
3. t
SKEWPR
is the skew between a pair of outputs (xQ
0
and xQ
1
) when all eight outputs are selected for 0t
U
.
4. t
SKEW0
is the skew between outputs when they are selected for 0t
U
.
5. For IDT5991A-2 t
SKEW0
is measured with C
L
= 0pF; for C
L
= 30pF, t
SKEW0
= 0.35ns Max.
6. There are 3 classes of outputs: Nominal (multiple of t
U
delay), Inverted (4Q
0
and 4Q
1
only with 4F
0
= 4F
1
= HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-
by-4 mode).
7. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
8. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
9. t
PD
is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns.
wince5.0系统，启动中死在这里FMD_GetBlockStatus::Logical block 0x4BF is marked as bad
信息有：
-OALTimerInit
pDrvGlobalArea->bEboot == TRUE. Forcing Clean Object store
+OEMPower ......
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