D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
74ACTQ16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
June 1991
Revised May 2005
74ACTQ16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ16374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.
The ACTQ16245 utilizes Fairchild Quiet Series
¥
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series
¥
fea-
tures GTO
¥
output control for superior performance.
Features
s
Utilizes Fairchild FACT Quiet Series technology
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Buffered Positive edge-triggered clock
s
Separate control logic for each byte
s
16-bit version of the ACTQ374
s
Outputs source/sink 24 mA
s
Additional specs for Multiple Output Switching
s
Output loadings specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ16374SSC
74ACTQ16374MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
Pin Descriptions
Pin
Description
Names
OE
n
CP
n
I
0
–I
15
O
0
–O
15
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT
¥
, FACT Quiet Series
¥
and GTO
¥
are trademarks of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010935
www.fairchildsemi.com
74ACTQ16374
Functional Description
The ACTQ16374 consists of sixteen edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The device is byte controlled with each byte function-
ing identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP
n
)
transition. With the Output Enable (OE
n
) LOW, the con-
tents of the flip-flops are available at the outputs. When
OE
n
is HIGH, the outputs go to the high impedance state.
Operation of the OE
n
input does not affect the state of the
flip-flops.
Truth Tables
Inputs
CP
1
Outputs
I
0
–I
7
H
L
X
X
O
0
–O
7
H
L
(Previous)
Z
Outputs
I
8
–I
15
H
L
X
X
O
8
–O
15
H
L
(Previous)
Z
OE
1
L
L
L
H
Inputs
CP
2
L
X
L
X
OE
2
L
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z HIGH Impedance
LOW-to-HIGH Transition
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
www.fairchildsemi.com
2
74ACTQ16374
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
V
O
V
O
0.5V to
7.0V
20 mA
20 mA
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
0.5V
V
CC
0.5V
0.5V
V
CC
0.5V
DC Output Diode Current (I
OK
)
40
q
C to
85
q
C
125 mV/ns
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin
Storage Temperature
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZ
I
IN
I
CCT
I
CC
I
OLD
I
OHD
V
OLP
V
OLV
V
OHP
V
OHV
V
IHD
V
ILD
Maximum 3-STATE
Leakage Current
Maximum Input Leakage Current
Maximum I
CC
/Input
Maximum Quiescent Supply Current
Minimum Dynamic
Output Current (Note 3)
Quiet Output Maximum
Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Maximum Overshoot
Minimum V
CC
Droop
Minimum HIGH Dynamic Input Voltage Level
Maximum LOW Dynamic Input Voltage Level
5.0
5.0
5.0
5.0
5.0
5.5
5.5
5.5
5.5
5.0
0.5
0.8
0.6
8.0
5.5
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Guaranteed Limits
Units
V
V
V
V
OUT
V
OUT
I
OUT
V
IN
V
I
OH
I
OH
V
I
OUT
V
IN
V
I
OL
I
OL
V
I
V
O
V
I
V
I
V
IN
V
OLD
Conditions
0.1V
0.1V
or V
CC
0.1V
or V
CC
0.1V
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 2)
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 2)
V
IL
, V
IH
V
CC
, GND
V
CC
, GND
V
CC
2.1V
V
CC
or GND
1.65V Max
3.85V Min
r
0.5
r
0.1
r
5.0
r
1.0
1.5
80.0
75
P
A
P
A
mA
P
A
mA
mA
V
75
V
OHD
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
(Note 4)(Note 7)
(Note 4)(Note 7)
0.5
1.0
V
V
V
V
V
V
OH
1.0 V
OH
1.5
V
OH
1.0 V
OH
1.8
1.7
1.2
2.0
0.8
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms; one output loaded at a time.
Note 4:
Worst case package.
Note 5:
Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched LOW and one output held LOW.
Note 6:
Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched HIGH and one output held HIGH.
Note 7:
Maximum number of data inputs (n) switching. (n
1) input switching 0V to 3V (ACTQ). Input under test switching 3V to threshold (V
ILD
).
3
www.fairchildsemi.com
74ACTQ16374
AC Electrical Characteristics
V
CC
Symbol
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Note 8:
Voltage Range 5.0 is 5.0V
r
0.5V.
T
A
C
L
Min
71
3.1
3.0
2.5
3.0
2.1
2.0
25
q
C
50 pF
Typ
5.3
5.1
4.7
5.4
5.1
4.8
Max
7.9
7.3
7.4
8.0
7.9
7.4
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
MHz
8.4
7.8
7.9
8.5
8.2
7.9
ns
ns
ns
Units
Parameter
Maximum Clock Frequency
Propagation Delay
CP to O
n
Output Enable Time
Output Disable Time
(V)
(Note 8)
5.0
5.0
5.0
5.0
Min
67
3.1
3.0
2.5
2.0
2.1
2.0
AC Operating Requirements
V
CC
Symbol
t
S
t
H
t
W
Parameter
Setup Time, HIGH or LOW
Input to Clock
Hold Time, HIGH or LOW
Input to Clock
CP Pulse Width,
HIGH or LOW
Note 9:
Voltage Range 5.0 is 5.0V
r
0.5V.
T
A
C
L
Typ
0.7
0.8
1.5
25
q
C
50 pF
T
A
40
q
C to
85
q
C
C
L
50 pF
Units
ns
ns
ns
(V)
(Note 9)
5.0
5.0
5.0
Guaranteed Limits
3.0
1.0
5.0
3.0
1.0
5.0
www.fairchildsemi.com
4
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
