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74ABT646 Octal Transceivers and Registers with 3-STATE Outputs
April 1992
Revised November 1999
74ABT646
Octal Transceivers and Registers with 3-STATE Outputs
General Description
The ABT646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
Features
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data
s
A and B output sink capability of 64 mA, source capabil-
ity of 32 mA
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and 250 pF
loads
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Order Number
74ABT646CSC
74ABT646CMSA
74ABT646CMTC
Package Number
M24B
MSA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 4.4mm Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A
0
–A
7
B
0
–B
7
CPAB, CPBA
SAB, SBA
OE
DIR
Description
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
© 1999 Fairchild Semiconductor Corporation
DS010978
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74ABT646
Truth Table
Inputs
OE
H
H
H
L
L
L
L
L
L
L
L
DIR
X
X
X
H
H
H
H
L
L
L
L
CPAB
H or L
CPBA
H or L
SAB
X
X
X
L
L
H
H
X
X
X
X
SBA
X
X
X
X
X
X
X
L
L
H
H
Output
Input
Input
Input
Input
Data I/O
(Note 1)
A
0
–A
7
B
0
–B
7
Isolation
Clock A
n
Data into A Register
Clock B
n
Data into B Register
A
n
to B
n
—Real Time (Transparent Mode)
Output Clock A
n
Data into A Register
A Register to B
n
(Stored Mode)
Clock A
n
Data into A Register and Output to B
n
B
n
to A
n
—Real Time (Transparent Mode)
Clock B
n
Data into B Register
B Register to A
n
(Stored Mode)
Clock B
n
Data into B Register and Output to A
n
Function
X
X
X
X
X
X
H or L
X
X
X
X
X
H or L
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
Note 1:
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Real Time Transfer
A-Bus to B-Bus
Storage from
Bus to Register
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
FIGURE 3.
Transfer from
Register to Bus
FIGURE 2.
FIGURE 4.
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2
74ABT646
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74ABT646
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Any Output
in the Disable or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
Over Voltage Latchup (I/O)
twice the rated I
OL
(mA)
−500
mA
10V
−0.5V
to
+5.5V
−0.5V
to V
CC
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (∆V/∆t)
Data Input
Enable Input
Clock Input
50 mV/ns
20 mV/ns
100 mV/ns
−40°C
to
+85°C
+4.5V
to
+5.5V
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
V
ID
I
IH
I
BVI
I
BVIT
I
IL
I
IH
+
I
OZH
I
IL
+
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
I
CCD
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Test
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
4.75
1
1
7
100
−1
−1
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Dynamic I
CC
(Note 4)
No Load
0.18
mA/MHz
Max
−100
10
−10
−275
50
100
250
30
50
2.5
2.5
2.0
0.55
V
0.0
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
= −18
mA (Non I/O Pins)
I
OH
= −3
mA, (A
n
, B
n
)
I
OH
= −32
mA, (A
n
, B
n
)
I
OL
=
64 mA, (A
n
, B
n
)
I
ID
=
1.9
µA,
(Non-I/O Pins)
All Other Pins Grounded
µA
µA
µA
µA
µA
µA
mA
µA
µA
µA
mA
µA
mA
Max
Max
Max
Max
V
IN
=
2.7V (Non-I/O Pins) (Note 4)
V
IN
=
V
CC
(Non-I/O Pins)
V
IN
=
7.0V (Non-I/O Pins)
V
IN
=
5.5V (A
n
, B
n
)
V
IN
=
0.5V (Non-I/O Pins) (Note 4)
V
IN
=
0.0V (Non-I/O Pins)
0V–5.5V V
OUT
=
2.7V (A
n
, B
n
); OE
=
2.0V
0V–5.5V V
OUT
=
0.5V (A
n
, B
n
); OE
=
2.0V
Max
Max
0.0V
Max
Max
Max
Max
V
OUT
=
0V (A
n
, B
n
)
V
OUT
=
V
CC
(A
n
, B
n
)
V
OUT
=
5.5V (A
n
, B
n
);
All Others GND
All Outputs HIGH
All Outputs LOW
Outputs 3-STATE; All Others GND
V
I
=
V
CC
−
2.1V
All Other Outputs at V
CC
or GND
Outputs OPEN
OE and DIR
=
GND,
Non-I/O
=
GND or V
CC
(Note 5)
One Bit toggling, 50% duty cycle
Note 4:
Guaranteed but not tested.
Note 5:
For 8-bit toggling, I
CCD
<
1.4 mA/MHz.
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