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74ABT573 Octal D-Type Latch with 3-STATE Outputs
January 1993
Revised March 2005
74ABT573
Octal D-Type Latch with 3-STATE Outputs
General Description
The ABT573 is an octal latch with buffered common Latch
Enable (LE) and buffered common Output Enable (OE)
inputs.
This device is functionally identical to the ABT373 but has
broadside pinouts.
Features
s
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s
Useful as input or output port for microprocessors
s
Functionally identical to ABT373
s
3-STATE outputs for bus interfacing
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and 250 pF
loads
s
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch-free bus loading during entire
power up and power down
s
Nondestructive hot insertion capability
Ordering Code:
Order Number
74ABT573CSC
74ABT573CSCX_NL
(Note 1)
74ABT573CSJ
74ABT573CMSA
74ABT573CMTC
74ABT573CMTCX_NL
(Note 1)
74ABT573CPC
Package
Number
M20B
M20B
M20D
MSA20
MTC20
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS011548
www.fairchildsemi.com
74ABT573
Connection Diagram
Functional Description
The ABT573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input (Active HIGH)
3-STATE Output Enable Input (Active LOW)
3-STATE Latch Outputs
Descriptions
Function Table
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
O
H
L
O
0
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
O
0
Value stored from previous clock cycle
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ABT573
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
Over Voltage Latchup (I/O)
Twice the rated I
OL
(mA)
65
q
C to
150
q
C
55
q
C to
125
q
C
55
q
C to
150
q
C
0.5V to
7.0V
0.5V to
7.0V
30 mA to
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
40
q
C to
85
q
C
4.5V to
5.5V
0.5V to
5.5V
0.5V to V
CC
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs.
500 mA
10V
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input LOW Current
Input Leakage Test
4.75
2.5
2.0
0.55
1
1
7
Min
2.0
0.8
Typ
Max
Units
V
V
V
V
V
Min
Min
Min
Max
Max
Max
0.0
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
I
OH
I
OH
I
OL
V
IN
V
IN
V
IN
V
IN
V
IN
I
ID
1.2
18 mA
3 mA
32 mA
64 mA
2.7V (Note 5)
V
CC
7.0V
0.5V (Note 5)
0.0V
1.9
P
A
P
A
P
A
P
A
V
1
1
All Other Pins Grounded
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
I
CCD
Dynamic I
CC
(Note 5)
Note 4:
For 8 bits toggling, I
CCD
0.8 mA/MHz.
Note 5:
Guaranteed but not tested.
10
P
A
P
A
mA
0
5.5V V
OUT
0
5.5V V
OUT
Max
Max
0.0
Max
Max
Max
V
OUT
V
OUT
V
OUT
2.7V; OE
0.5V; OE
0.0V
V
CC
2.0V
2.0V
10
100
275
50
100
50
30
50
2.5
2.5
2.5
P
A
P
A
P
A
mA
5.5V; All Others GND
All Outputs HIGH
All Outputs LOW
OE
V
I
V
CC
V
CC
2.1V
V
CC
2.1V
V
CC
2.1V
P
A
mA
mA
mA
mA/
All Others at V
CC
or GND
Max
Enable Input V
I
Data Input V
I
Max
Outputs Open
OE
GND, LE
V
CC
(Note 4)
One Bit Toggling, 50% Duty Cycle
All Others at V
CC
or GND
No Load
0.12
MHz
3
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74ABT573
DC Electrical Characteristics
Symbol
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Min
Typ
0.7
Max
1.0
Units
V
V
V
V
0.7
V
V
CC
5.0
5.0
5.0
5.0
5.0
T
A
T
A
T
A
T
A
T
A
Conditions
C
L
50 pF, R
L
500
:
25
q
C (Note 6)
25
q
C (Note 6)
25
q
C (Note 7)
25
q
C (Note 8)
25
q
C (Note 8)
1.5
2.5
2.2
1.2
3.0
1.8
1.0
Note 6:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 8:
Max number of data inputs (n) switching. n
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
T
A
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Time
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
1.9
1.9
2.0
2.0
1.5
1.5
2.0
2.0
V
CC
C
L
25
q
C
5.0V
50 pF
Typ
2.7
2.8
3.1
3.0
3.1
3.1
3.6
3.4
Max
4.5
4.5
5.0
5.0
5.3
5.3
5.4
5.4
T
A
V
CC
40
q
C to
85
q
C
4.5V to 5.5V
50 pF
Max
4.5
4.5
5.0
5.0
5.3
5.3
5.4
5.4
ns
ns
ns
ns
Units
C
L
Min
1.9
1.9
2.0
2.0
1.5
1.5
2.0
2.0
AC Operating Requirements
(SOIC and SSOP Package)
T
A
Symbol
Parameter
Min
f
TOGGLE
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
Max Toggle Frequency
Set Time, HIGH
or LOW D
n
to LE
Hold Time, HIGH
or LOW D
n
to LE
Pulse Width,
LE HIGH
1.5
1.5
1.0
1.0
3.0
V
CC
C
L
25
q
C
5.0V
50 pF
Typ
100
Max
T
A
V
CC
40
q
C to
85
q
C
4.5V to 5.5V
50 pF
Max
MHz
Units
C
L
Min
1.5
1.5
1.0
1.0
3.0
ns
ns
ns
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