TM
82C85
CMOS Static Clock Controller/Generator
Description
The Intersil 82C85 Static CMOS Clock Controller/Genera-
tor provides complete control of static CMOS system oper-
ating modes and supports full speed, slow, stop-clock and
stop-oscillator operation. While directly compatible with the
Intersil 80C86 and 80C88 16-bit Static CMOS Microproces-
sor Family, the 82C85 can also be used for general system
clock control.
For static system designs, separate signals are provided
on the 82C85 for stop (S0, S1, S2/STOP) and start
(START) control of the crystal oscillator and system clocks.
A single control line (SLO/FST) determines 82C85 fast
(crystal/EFI frequency divided by 3) or slow (crystal/EFI
frequency divided by 768) mode operation. Automatic
maximum mode 80C86 and 80C88 software HALT
instruction decode logic in the 82C85 enables software-
based clock control. Restart logic insures valid clock start-
up and complete synchronization of system clocks.
The 82C85 is manufactured using the Intersil advanced
Scaled SAJI IV CMOS process. In addition to clock control
circuitry, the 82C85 also contains a crystal controlled
oscillator (up to 25MHz), clock generation logic, complete
“Ready” synchronization and reset logic. This permits the
designer to tailor the system power-performance product to
provide optimum performance at low power levels.
March 1997
Features
• Generates the System Clock For CMOS or NMOS
Microprocessors and Peripherals
• Complete Control Over System Operation for Very
Low System Power
- Stop-Oscillator
- Low Frequency
- Stop-Clock
- Full Speed Operation
• DC to 25MHz Operation (DC to 8MHz System Clock)
• Generates 50% and 33% Duty Cycle Clocks
(Synchronized)
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• TTL Compatible Inputs/Outputs
• 24 Lead Slimline Dual-In-Line or 28 Pad Square LCC
Package Options
• Single 5V Power Supply
• Operating Temperature Range
- C82C85 . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
- I82C85 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C85 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Ordering Information
PART NUMBER
CS82C85
IS82C85
CD82C85
ID82C85
MD82C85/B
MR82C85/B
28 Pad CLCC
24 Ld CERDIP
PACKAGE
28 Ld PLCC
TEMP. RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
PKG. NO.
N28.45
N28.45
F24.3
F24.3
F24.3
J28.A
Pinouts
24 LEAD CERDIP
TOP VIEW
CSYNC
1
PCLK
2
AEN1
3
RDY1
4
READY
5
RDY2
6
AEN2
7
CLK
8
GND
9
CLK50
10
START
11
SLO/FST
12
24
V
CC
23
X1
22
X2
21
ASYNC
20
EFI
19
F/C
18
OSC
17
RES
16
RESET
15
S2/STOP
14
S1
13
S0
28 LEAD PLCC, CLCC
TOP VIEW
AEN1
PCLK
CSYNC
NC
V
CC
X1
S0
S1
X2
25
NC
24
ASYNC
23
EFI
22
F/C
21
OSC
20
RES
19
RESET
12 13 14 15 16 17 18
4
3
2
1 28 27 26
RDY1
READY
RDY2
AEN2
CLK
GND
NC
5
6
7
8
9
10
11
CLK50
START
SLO/FST
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
S2/STOP
FN2976.1
297
82C85
Pin Descriptions
SYMBOL
X1
X2
DIP PIN
NUMBER
23
22
TYPE
I
O
DESCRIPTION
CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystal frequency
must be 3 times the maximum desired processor clock frequency. X1 is the oscillator circuit input
and X2 is the output of the oscillator circuit. If the crystal inputs are not used, X1 must be tied to V
CC
or GND, and X2 should be left open.
EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input signal. This
input signal should be a square wave with a frequency of three times the maximum desired CLK
output frequency. If the crystal inputs are not used. XI must be tied to V
CC
or GND, and X2 should
be left open.
FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI input as the
main frequency source. When F/C is LOW, the 82C85 clocks are derived from the crystal oscillator
circuit. When F/C is HIGH, CLK is generated from the EFI input. F/C cannot be dynamically
switched during normal operation.
A low-to-high transition on START will restart the CLK, CLK50 and PCLK outputs after the appro-
priate restart sequence is completed.
When in the crystal mode (F/C LOW) with the oscillator stopped. The oscillator will be restarted
when a Start command is received. The CLK, CLK50 and PCLK outputs will start after the oscillator
input signal (X1) reaches the Schmitt trigger input threshold and 8K internal counter reaches termi-
nal count. If F/C is HIGH (EFI mode), CLK, CLK50 and PCLK will restart within 3 EFI cycles after
START is recognized.
The 82C85 will restart in the same mode (SLO/FST) in which it stopped. A high level on START
disables the STOP mode.
SO
S1
S2/STOP
13
14
15
I
I
I
S2/STOP, S1, SO are used to stop the 82C85 clock outputs (CLK, CLK50, PCLK) and are sampled
by the rising edge of CLK, CLK50 and PCLK are stopped by S2/STOP, S1, SO being in the LHH
state on the low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring
on the previous low-to-high CLK transition. CLK and CLK50 stop in the high state when F/C is low
and may stop in either the high or low state when F/C is high. PCLK stops in its current state (high
or low).
When in the crystal mode (F/C) low and a STOP command is issued, the 82C85 oscillator will stop along
with the CLK, CLK50 and PCLK outputs. When in the EFI mode, only the CLK, CLK50 and PCLK out-
puts will be halted. The oscillator circuit if operational, will continue to run. The oscillator and/or clock is
restarted by the START input signal going true (HIGH) or the reset input (RES) going low.
SLO/FST
12
I
SLO/FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the maximum
frequency (crystal or EFI frequency divided by 3). When LOW, CLK and CLK50 frequencies are
equal to the crystal or EFI frequency divided by 768. SLO/FST changes are internally synchronized
so proper CLK and CLK50 phase relationships are maintained and minimum pulse width specifica-
tions are met. START and STOP control of the oscillator or EFI is available in either the SLOW or
FAST frequency modes. The SLO/FST input must be held LOW for at least 195 OSC/EFI clock cy-
cles before it will be recognized. This eliminates unwanted frequency changes which could be
caused by glitches or noise transients. The SLO/FST input must be held HIGH for at least 6
OSC/EFI clock pulses to guarantee a transition to FAST mode operation.
PROCESSOR CLOCK: CLK is the clock output used by the 80C86 or 80C88 processor and other
peripheral devices. When SLO/FST is high, CLK has an output frequency which is equal to the crys-
tal or EFI input frequency divided by three. When SLO/FST is low, CLK has an output frequency
which is equal to the crystal or EFI input frequency divided by 768. CLK has a 33% duty cycle.
50% DUTY CYCLE CLOCK: CLK50 is an auxiliary clock with a 50% duty cycle and is synchronized
to the falling edge of CLK. When SLO/FST is high, CLK50 has an output frequency which is equal
to the crystal or EFI input frequency divided by 3. When SLO/FST is low, CLK50 has an output fre-
quency equal to the crystal or EFI input frequency divided by 768.
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is equal to the
crystal or EFI input frequency divided by 6 and has a 50% duty cycle. PCLK frequency is unaffected
by the state of the SLO/FST input.
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal
to that of the crystal oscillator circuit. OSC is unaffected by the state of the SLO/FST input.
When the 82C85 is in the crystal mode (F/C low) and a STOP command is issued, the OSC output
will stop in the HIGH state. When the 82C85 is in the EFI mode (F/C HIGH, the oscillator (if
operational) will continue to run when a STOP command is issued and OSC remains active.
EFI
20
I
F/C
19
I
START
11
I
CLK
8
O
CLK50
10
O
PCLK
2
O
OSC
18
O
298
82C85
Pin Descriptions
SYMBOL
RES
DIP PIN
NUMBER
17
(Continued)
TYPE
I
DESCRIPTION
RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C85 provides a
Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper
duration. RES starts crystal oscillator operation.
RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its
timing characteristics are determined by RES. RESET is guaranteed to be HIGH for a minimum of
16 CLK pulses after the rising edge of RES.
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C85 and
82C84A to be synchronized to provide multiple in-phase clock signals When CSYNC is HIGH, the
internal counters are reset and force CLK, CLK50 and PCLK into a HIGH state. When CSYNC is
LOW, the internal counters are allowed to count and the CLK, CLK50 and PCLK outputs are active.
CSYNC must be externally synchronized to EFI.
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready
Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs
are useful in system configurations which permit the processor to access two Multi-Master System
Buses.
BUS READY: (Transfer Complete). RDY is an active HIGH signal which is an indication from a de-
vice located on the system data bus that data has been received, or is available RDY1 is qualified
by AEN1 while RDY2 is qualified by AEN2.
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization
mode of the READY logic. When ASYNC is LOW, two stages of READY synchronization are pro-
vided. When ASYNC is left open or HIGH a single stage of READY synchronization is provided.
READY: READY is an active HIGH signal which is the synchronized RDY signal input.
Ground
V
CC
: is the +5V power supply pin. A 0.1mF capacitor between V
CC
and GND is recommended.
RESET
16
O
CSYNC
1
I
AEN1
AEN2
3
7
I
I
RDY1
RDY2
ASYNC
4
6
21
I
I
I
READY
GND
V
CC
5
9
24
O
I
I
Functional Block Diagram
RES
(17)
START
(11)
(1)
(12)
F/C
EFI
CSYNC
SLO/FST
SPEED SELECT
DIV 256 OR DIV 1
EXTERNAL
FREQ.
SELECT
OSC
SELECTED
OSC
MASTER
OSC
RESTART
LOGIC
RESET PULSE
CONDITIONING
LOGIC
RESTART
SYNC
LOGIC
SYNC
CLOCK
LOGIC
(DIVIDE
BY 3)
CLK
(8)
(16)
RESET
(10)
CLK50
(2)
PCLK
(19)
(20)
PERIPHERAL
CLOCK
(DIVIDE BY 6)
(22)
(23)
X2
X1
OSCILLATOR
OSC
S2/STOP
(18)
(15)
(14)
(13)
S1
S0
RDY1
STOP LOGIC
HALT
(4)
(3)
(7)
(6)
(21)
AEN1
AEN2
RDY2
ASYNC
READY
SELECT
READY
SYNC
V
CC
(24)
GND (9)
(5)
READY
299
82C85
Functional Description
The 82C85 Static Clock Controller/Generator provides sim-
ple and complete control static CMOS system operating
modes. The 82C85 supports full speed, slow, stop-clock and
stop-oscillator operation. While it is directly compatible with
the Intersil 80C86 and 80C88 CMOS 16-bit static micropro-
cessors, the 82C85 can also be used for general purpose
system clock control.
The 82C85 pinout is a superset of the 82C84A Clock Gener-
ator/Driver. 82C85 pins 1-9, 16-24 are compatible with
82C84A pins 1-9, 10-18 respectively. An 82C84A can be
placed in the upper 18 pins of an 82C85 socket and it will
operate correctly (without the ability to control the clock and
oscillator operation.) This allows dual design for simple sys-
tem upgrades. The 82C85 will also emulate an 82C84A
when pins 11-15 on the 82C85 are tied to V
CC
.
For static systems designs, separate signals are provided on
the 82C85 for stop and start control of the crystal oscillator
and clock outputs. A single control line determines 82C85
fast (crystal/EFI frequency divided by 3) or slow (crystal/EFI
frequency divided by 768) mode operation. The 82C85 also
contains a crystal controlled oscillator, clock generation
logic, complete “Ready” synchronization and reset logic.
Automatic 80C86/88 software HALT instruction decode logic
is present to ease the design of software-based clock control
systems and provide complete software control of STOP
mode operation. Restart logic insures valid clock start-up
and complete synchronization of CLK, CLK50 and PCLK.
Static Operating Modes
In static CMOS system design, there are four basic operat-
ing modes. The 82C85 Static Clock Controller supports each
of them. These modes are: FAST, SLOW, STOP-CLOCK
and STOP-OSCILLATOR. Each has distinct power and per-
formance characteristics which can be matched to the needs
of a particular system at a specific time (See Table 1).
Keep in mind that a single system may require all of these
operating modes at one time or another during normal opera-
tion. A design need not be limited to a single operating mode
or a specific combination of modes. The appropriate operating
mode can be matched to the power-performance level
needed at a specific time or in a particular circumstance.
Reset Logic
The 82C85 reset logic provides a Schmitt trigger input (RES)
and a synchronizing flip-flop to generate the reset timing.
The reset signal is synchronized to the falling edge of CLK.
A simple RC network can be used to provide power-on reset
by utilizing this function of the 82C85.
When in the crystal oscillator (F/C = LOW) or the EFI (F/C =
HIGH) mode, a LOW state on the RES input will set the
RESET output to the HIGH state. It will also restart the oscil-
lator circuit if it is in the idle state. The RESET output is guar-
anteed to stay in the HIGH state for a minimum of 16 CLK
cycles after a low-to-high transition of the RES input.
An oscillator restart count sequence will not be disturbed by
RESET if this count is already in progress. After the restart
counter expires, the RESET output will stay HIGH at least for
16 periods of CLK before going LOW. RESET can be kept high
beyond this time by a continuing low input on the RES input.
If F/C is low (crystal oscillator mode), a low state on RES
starts the crystal oscillator circuit. The stopped outputs
remain inactive, until the oscillator signal amplitude reaches
the X1 Schmitt trigger input threshold voltage and 8192
cycles of the crystal oscillator output are counted by an inter-
nal counter. After this count is complete, the stopped outputs
(CLK, CLK50, PCLK, and OSC) start cleanly with the proper
phase relationships.
This 8192 count requirement insures that the CLK, CLK50
and PCLK outputs will meet minimum clock requirements
and will not be affected by unstable oscillator characteristics
which may exist during the oscillator start-up sequence. This
sequence is also followed when a START command is
issued while the 82C85 oscillator is stopped.
Oscillator/Clock Start Control
Once the oscillator is stopped (or committed to stop) or at power-
on, the restart sequence is initiated by a HIGH state on START
or LOW state on RES. If F/C is HIGH, then restart occurs imme-
diately after the START or RES input is synchronized internally.
This insures that stopped outputs (CLK, PCLK, OSC and
CLK50) start cleanly with the proper phase relationship.
If F/C is low (crystal oscillator mode), a HIGH state on the
START input or a low state on RES causes the crystal oscil-
lator to be restarted. The stopped outputs remain stopped,
TABLE 1. STATIC SYSTEM OPERATING MODE CHARACTERISTICS
OPERATING
MODE
Stop-Oscillator
DESCRIPTION
All system clocks and main clock oscillator are
stopped
System CPU and peripherals clocks stop but main
clock oscillator continues to run at rated frequency
System CPU clocks are slowed while peripheral clock
and main clock oscillator run at rated frequency
POWER LEVEL
Maximum Savings
PERFORMANCE
Slowest response due to oscillator
restart time
Fast restart-no oscillator restart time
Stop-Clock
Reduced System
Power
Power Dissipation
Slightly Higher Than
Stop-Clock
Highest Power
Slow
Continuous operation at low frequency
Fast
All clocks and oscillators run at rated frequency
Fastest response
300
82C85
until the oscillator signal amplitude reaches the X1 Schmitt
trigger input threshold voltage and 8192 cycles of the crystal
oscillator output are counted by an internal counter. After
this count is complete, the stopped outputs (CLK, CLK50,
PCLK, and OSC) start cleanly with the proper phase rela-
tionships.
Typically, any input signal which meets the START input tim-
ing requirements can be used to start the 82C85. In many
cases, this would be the INT output from an 82C59A CMOS
Priority Interrupt Controller (See Figure 1). This output,
which is active high, can be connected to both the 82C85
START pin and to the appropriate interrupt request input on
the microprocessor.
80C86/88
INTR
82C85
82C59A
INT
CLK
V
CC
START S0
S1
S2/STOP
SLO/FST
CLK
When the INT output becomes active, the oscillator/clock cir-
cuit on the 82C85 will restart. Upon completion of the appro-
priate restart sequence, the CLK signal to the CPU will
become active. The CPU can then respond to the still pend-
ing interrupt request.
If the 82C59A/82C85 restart combination is used in conjunc-
tion with an 82C55A STOP control, the 82C55A must be ini-
tialized prior to the 82C59A after reset. The 82C59A
interrupt output is driven high at reset, causing the 82C85 to
remain in the START mode regardless of the state of the
S2/STOP input. This will avoid stopping the 82C85 due to
negative transitions on the S2/STOP input which may occur
during a mode change on the 82C55A or during the opera-
tion of any peripheral I/O device prior to initialization.
Another method of insuring proper operation of the START
function upon reset or system initialization is to bias the
S2/STOP input low with an external pull-down resistor. The
S2/STOP input will remain low until driven high by the
82C55A port pin or by external logic. This insures that the
82C85 STOP command (HHH prior to LHH requirement on
the status inputs) will not be satisfied. To minimize power
dissipation in this case (using a pulldown resistor), the
S2/STOP input should be normally LOW and pulsed HIGH
to develop the necessary HHH-to-LHH STOP sequence. In
this manner, the output driving the S2/STOP input will be
normally LOW and will not be driving to the opposite state of
the pull-down resistor.
Fast Mode
The most common operating mode for a system is the FAST
mode. In this mode, the 82C85 operates at the maximum fre-
quency determined by the main oscillator or EFI frequency.
PA0 PA1
82C55A
FIGURE 1. CMOS PERIPHERAL CONTROL OF 82C85 STOP,
START AND SLOW/FAST OPERATIONS
TABLE 2. TYPICAL SYSTEM POWER SUPPLY CURRENT FOR STATIC CMOS OPERATING MODES
FAST
CPU Frequency
XTAL Frequency
ICC
82C85
80C88
82C82
82C86
82C88
82C52
82C54
82C55A
82C59A
74HCXX + other
HM-6516
HM-6616
Total
24.7mA
23.8mA
1.7mA
1.4mA
3.5mA
151.2mA
943.0mA
3.2mA
580.0mA
2.9mA
820.0mA
6.3mA
66.8mA
16.9mA
173.0mA
6.5mA
14.0mA
14.3mA
72.0mA
915.0mA
1.2mA
520.0mA
10.0mA
32.0mA
52.5mA
18.9mA
14.1mA
106.6mA
1.0mA
1.0mA
3.8mA
1.0mA
3.5mA
1.0mA
1.0mA
90.0mA
1.9mA
12.0mA
14.3mA
24.4mA
106.6mA
1.0mA
1.0mA
3.8mA
1.0mA
1.0mA
1.0mA
1.0mA
90.0mA
1.9mA
12.0mA
244.7mA
5MHz
15MHz
SLOW
20 KHz
15MHz
STOP-CLOCK
DC
15MHz
STOP-OSC
DC
DC
All measurements taken at room temperature, V
CC
= +5.0V. Power supply current levels will be dependent upon system configuration and
frequency of operation.
301
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